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the Vahalia' "Unix Internals" section 15.12 "Other TLB Consistency Algorithms". The same algorithm is already utilized by the MIPS pmap to handle ASIDs. The PCID for the address space is now allocated per-cpu during context switch to the thread using pmap, when no PCID on the cpu was ever allocated, or the current PCID is invalidated. If the PCID is reused, bit 63 of %cr3 can be set to avoid TLB flush. Each cpu has PCID' algorithm generation count, which is saved in the pmap pcpu block when pcpu PCID is allocated. On invalidation, the pmap generation count is zeroed, which signals the context switch code that already allocated PCID is no longer valid. The implication is the TLB shootdown for the given cpu/address space, due to the allocation of new PCID. The pm_save mask is no longer has to be tracked, which (significantly) reduces the targets of the TLB shootdown IPIs. Previously, pm_save was reset only on pmap_invalidate_all(), which made it accumulate the cpuids of all processors on which the thread was scheduled between full TLB shootdowns. Besides reducing the amount of TLB shootdowns and removing atomics to update pm_saves in the context switch code, the algorithm is much simpler than the maintanence of pm_save and selection of the right address space in the shootdown IPI handler. Reviewed by: alc Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 3 weeks |
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_align.h | ||
_inttypes.h | ||
_limits.h | ||
_stdint.h | ||
_types.h | ||
acpica_machdep.h | ||
apicreg.h | ||
apicvar.h | ||
apm_bios.h | ||
bus.h | ||
busdma_impl.h | ||
dump.h | ||
elf.h | ||
endian.h | ||
fdt.h | ||
float.h | ||
fpu.h | ||
frame.h | ||
init.h | ||
legacyvar.h | ||
mca.h | ||
mptable.h | ||
ofw_machdep.h | ||
pci_cfgreg.h | ||
psl.h | ||
ptrace.h | ||
pvclock.h | ||
reg.h | ||
segments.h | ||
setjmp.h | ||
sigframe.h | ||
signal.h | ||
specialreg.h | ||
stdarg.h | ||
sysarch.h | ||
trap.h | ||
ucontext.h | ||
vdso.h | ||
vmware.h |