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82645a84eb
better or worse. Ok'd by folks that have additional copyrights to the files in cases where there's joint authorship.
85 lines
3.6 KiB
C
85 lines
3.6 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_RTCREG_H
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#define ARM_AT91_AT91_RTCREG_H
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/* Registers */
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#define RTC_CR 0x00 /* RTC Control Register */
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#define RTC_MR 0x04 /* RTC Mode Register */
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#define RTC_TIMR 0x08 /* RTC Time Register */
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#define RTC_CALR 0x0c /* RTC Calendar Register */
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#define RTC_TIMALR 0x10 /* RTC Time Alarm Register */
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#define RTC_CALALR 0x14 /* RTC Calendar Alarm Register */
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#define RTC_SR 0x18 /* RTC Status Register */
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#define RTC_SCCR 0x1c /* RTC Status Command Clear Register */
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#define RTC_IER 0x20 /* RTC Interrupt Enable Register */
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#define RTC_IDR 0x24 /* RTC Interrupt Disable Register */
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#define RTC_IMR 0x28 /* RTC Interrupt Mask Register */
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#define RTC_VER 0x2c /* RTC Valid Entry Register */
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/* TIMR */
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#define RTC_TIMR_SEC_M 0x7fUL
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#define RTC_TIMR_SEC_S 0
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#define RTC_TIMR_SEC(x) FROMBCD(((x) & RTC_TIMR_SEC_M) >> RTC_TIMR_SEC_S)
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#define RTC_TIMR_MIN_M 0x7f00UL
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#define RTC_TIMR_MIN_S 8
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#define RTC_TIMR_MIN(x) FROMBCD(((x) & RTC_TIMR_MIN_M) >> RTC_TIMR_MIN_S)
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#define RTC_TIMR_HR_M 0x3f0000UL
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#define RTC_TIMR_HR_S 16
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#define RTC_TIMR_HR(x) FROMBCD(((x) & RTC_TIMR_HR_M) >> RTC_TIMR_HR_S)
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#define RTC_TIMR_MK(hr, min, sec) \
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((TOBCD(hr) << RTC_TIMR_HR_S) | \
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(TOBCD(min) << RTC_TIMR_MIN_S) | \
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(TOBCD(sec) << RTC_TIMR_SEC_S))
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#define RTC_TIMR_PM (1UL << 22)
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/* CALR */
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#define RTC_CALR_CEN_M 0x0000007fUL
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#define RTC_CALR_CEN_S 0
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#define RTC_CALR_CEN(x) FROMBCD(((x) & RTC_CALR_CEN_M) >> RTC_CALR_CEN_S)
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#define RTC_CALR_YEAR_M 0x0000ff00UL
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#define RTC_CALR_YEAR_S 8
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#define RTC_CALR_YEAR(x) FROMBCD(((x) & RTC_CALR_YEAR_M) >> RTC_CALR_YEAR_S)
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#define RTC_CALR_MON_M 0x001f0000UL
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#define RTC_CALR_MON_S 16
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#define RTC_CALR_MON(x) FROMBCD(((x) & RTC_CALR_MON_M) >> RTC_CALR_MON_S)
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#define RTC_CALR_DOW_M 0x00d0000UL
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#define RTC_CALR_DOW_S 21
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#define RTC_CALR_DOW(x) FROMBCD(((x) & RTC_CALR_DOW_M) >> RTC_CALR_DOW_S)
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#define RTC_CALR_DAY_M 0x3f00000UL
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#define RTC_CALR_DAY_S 24
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#define RTC_CALR_DAY(x) FROMBCD(((x) & RTC_CALR_DAY_M) >> RTC_CALR_DAY_S)
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#define RTC_CALR_MK(yr, mon, day, dow) \
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((TOBCD((yr) / 100 + 19) << RTC_CALR_CEN_S) | \
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(TOBCD((yr) % 100) << RTC_CALR_YEAR_S) | \
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(TOBCD(mon) << RTC_CALR_MON_S) | \
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(TOBCD(dow) << RTC_CALR_DOW_S) | \
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(TOBCD(day) << RTC_CALR_DAY_S))
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#endif /* ARM_AT91_AT91_RTCREG_H */
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