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4e96bf3a37
The bwn(4) driver requires a number of extensions to the bhnd(4) PMU interface to support external configuration of PLLs, LDOs, and other parameters that require chipset or PHY-specific workarounds. These changes add support for: - Writing raw voltage register values to PHY-specific LDO regulator registers (required by LP-PHY). - Enabling/disabling PHY-specific LDOs (required by LP-PHY) - Writing to arbitrary PMU chipctrl registers (required for common PHY PLL reset support). - Requesting chipset/PLL-specific spurious signal avoidance modes. - Querying clock frequency and latency. Additionally, rather than updating legacy PWRCTL support to conform to the new PMU interface: - PWRCTL API is now provided by a bhnd_pwrctl_if.m interface. - Since PWRCTL is only found in older SSB-based chipsets, translation from bhnd(4) bus APIs to corresponding PWRCTL operations is now handled entirely within the siba(4) driver. - The PWRCTL-specific host bridge clock gating APIs in bhnd_bus_if.m have been lifted out into a standalone bhnd_pwrctl_hostb_if.m interface. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12664
103 lines
3.8 KiB
C
103 lines
3.8 KiB
C
/*-
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* Copyright (c) 2017 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Landon Fuller under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_BHND_PRIVATE_H_
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#define _BHND_BHND_PRIVATE_H_
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#include <sys/param.h>
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#include <sys/queue.h>
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#include "bhnd_types.h"
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/*
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* Private bhnd(4) driver definitions.
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*/
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/**
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* A bhnd(4) service registry entry.
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*/
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struct bhnd_service_entry {
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device_t provider; /**< service provider */
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bhnd_service_t service; /**< service implemented */
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uint32_t flags; /**< entry flags (see BHND_SPF_*) */
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volatile u_int refs; /**< reference count; updated atomically
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with only a shared lock held */
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STAILQ_ENTRY(bhnd_service_entry) link;
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};
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/**
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* bhnd(4) per-core PMU clkctl quirks.
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*/
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enum {
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/** On BCM4328-derived chipsets, the CLK_CTL_ST register CCS_HTAVAIL
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* and CCS_ALPAVAIL bits are swapped in the ChipCommon and PCMCIA
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* cores; the BHND_CCS0_* constants should be used. */
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BHND_CLKCTL_QUIRK_CCS0 = 1
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};
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/**
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* Per-core bhnd(4) PMU clkctl registers.
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*/
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struct bhnd_core_clkctl {
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device_t cc_dev; /**< core device */
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device_t cc_pmu_dev; /**< pmu device */
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uint32_t cc_quirks; /**< core-specific clkctl quirks */
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struct bhnd_resource *cc_res; /**< resource mapping core's clkctl register */
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bus_size_t cc_res_offset; /**< offset to clkctl register */
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u_int cc_max_latency; /**< maximum PMU transition latency, in microseconds */
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struct mtx cc_mtx; /**< register read/modify/write lock */
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};
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#define BHND_ASSERT_CLKCTL_AVAIL(_clkctl) \
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KASSERT(!bhnd_is_hw_suspended((_clkctl)->cc_dev), \
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("reading clkctl on suspended core will trigger system livelock"))
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#define BHND_CLKCTL_LOCK_INIT(_clkctl) mtx_init(&(_clkctl)->cc_mtx, \
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device_get_nameunit((_clkctl)->cc_dev), NULL, MTX_DEF)
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#define BHND_CLKCTL_LOCK(_clkctl) mtx_lock(&(_clkctl)->cc_mtx)
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#define BHND_CLKCTL_UNLOCK(_clkctl) mtx_unlock(&(_clkctl)->cc_mtx)
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#define BHND_CLKCTL_LOCK_ASSERT(_clkctl, what) \
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mtx_assert(&(_clkctl)->cc_mtx, what)
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#define BHND_CLKCTL_LOCK_DESTROY(_clkctl) mtx_destroy(&(_clkctl->cc_mtx))
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#define BHND_CLKCTL_READ_4(_clkctl) \
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bhnd_bus_read_4((_clkctl)->cc_res, (_clkctl)->cc_res_offset)
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#define BHND_CLKCTL_WRITE_4(_clkctl, _val) \
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bhnd_bus_write_4((_clkctl)->cc_res, (_clkctl)->cc_res_offset, (_val))
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#define BHND_CLKCTL_SET_4(_clkctl, _val, _mask) \
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BHND_CLKCTL_WRITE_4((_clkctl), \
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((_val) & (_mask)) | (BHND_CLKCTL_READ_4(_clkctl) & ~(_mask)))
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#endif /* _BHND_BHND_PRIVATE_H_ */
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