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287 lines
8.1 KiB
C
287 lines
8.1 KiB
C
/*-
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* Copyright (c) 1998, 1999 Scott Mitchell
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_xereg.h,v 1.2 1999/01/24 22:15:30 root Exp $
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*/
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/*
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* Register definitions for Xircom CreditCard Ethernet adapters. See if_xe.c
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* for details of supported hardware. Adapted from Werner Koch's 'xirc2ps'
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* driver for Linux.
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*/
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#include "xe.h"
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#if NXE > 0
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/*
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* Common registers
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*/
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#define XE_CR 0 /* Command register (write) */
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#define XE_ESR 0 /* Ethernet status register (read) */
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#define XE_PSR 1 /* Page select register */
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#define XE_EDP 4 /* Ethernet data port */
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#define XE_ISR 6 /* Interrupt status register */
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/*
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* Command register values
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*/
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#define XE_CR_TX_PACKET 0x01
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#define XE_CR_SOFT_RESET 0x02
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#define XE_CR_ENABLE_INTR 0x04
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#define XE_CR_FORCE_INTR 0x08
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#define XE_CR_CLEAR_FIFO 0x10
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#define XE_CR_CLEAR_OVERRUN 0x20
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#define XE_CR_RESTART_TX 0x40
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/*
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* Status register values
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*/
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#define XE_ESR_FULL_PKT_RX 0x01
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#define XE_ESR_PKT_REJECT 0x04
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#define XE_ESR_TX_PENDING 0x08
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#define XE_ESR_BAD_POLARITY 0x10
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#define XE_ESR_MEDIA_SELECT 0x20
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/*
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* Interrupt register values
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*/
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#define XE_ISR_TX_OVERFLOW 0x01
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#define XE_ISR_TX_PACKET 0x02
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#define XE_ISR_MAC_INTR 0x04
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#define XE_ISR_TX_RES 0x08
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#define XE_ISR_RX_PACKET 0x20
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#define XE_ISR_RX_REJECT 0x40
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#define XE_ISR_FORCE_INTR 0x80
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/*
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* Page 0 registers
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*/
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#define XE_TSO 8 /* Transmit space open */
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#define XE_TRS 10 /* Transmit reservation size */
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#define XE_DOR 12 /* Data offset register (write) */
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#define XE_RSR 12 /* Receive status register (read) */
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#define XE_PTR 13 /* Packets transmitted register (read) */
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#define XE_RBC 14 /* Received byte count (read) */
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/*
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* RSR values
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*/
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#define XE_RSR_PHYS_PKT 0x01
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#define XE_RSR_BCAST_PKT 0x02
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#define XE_RSR_LONG_PKT 0x04
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#define XE_RSR_ALIGN_ERR 0x10
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#define XE_RSR_CRC_ERR 0x20
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#define XE_RSR_RX_OK 0x80
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/*
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* Page 1 registers
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*/
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#define XE_IMR0 12 /* Interrupt mask register, part 1 */
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#define XE_IMR1 13 /* Interrupt mask register, part 2 */
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#define XE_ECR 14 /* Ethernet configuration register */
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/*
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* ECR values
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*/
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#define XE_ECR_FULL_DUPLEX 0x04
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#define XE_ECR_LONG_TPCABLE 0x08
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#define XE_ECR_NO_POLCOL 0x10
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#define XE_ECR_NO_LINKPULSE 0x20
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#define XE_ECR_NO_AUTOTX 0x40
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/*
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* Page 2 registers
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*/
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#define XE_RBS 8 /* Receive buffer start */
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#define XE_LED 10 /* LED configuration register */
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#define XE_MSR 12 /* Mohawk specfic register (Mohawk = CE3) */
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#define XE_GPR2 13 /* General purpose register 2 */
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/*
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* Page 4 registers
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*/
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#define XE_GPR0 8 /* General purpose register 0 */
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#define XE_GPR1 9 /* General purpose register 1 */
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#define XE_BOV 10 /* Bonding version register */
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#define XE_LMA 12 /* Local memory address */
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#define XE_LMD 14 /* Local memory data */
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/*
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* Page 5 registers
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*/
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#define XE_RHS 10 /* Receive host start address */
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/*
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* Page 0x40 registers
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*/
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#define XE_OCR 8 /* The Other command register */
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#define XE_RXS0 9 /* Receive status 0 */
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#define XE_TXS0 11 /* Transmit status 0 */
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#define XE_TXS1 12 /* Transmit status 1 */
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#define XE_RXM0 13 /* Receive mask register 0 */
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#define XE_TXM0 14 /* Transmit mask register 0 */
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#define XE_TXM1 15 /* Transmit mask register 1 */
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/*
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* OCR values
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*/
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#define XE_OCR_TX 0x01
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#define XE_OCR_RX_ENABLE 0x04
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#define XE_OCR_RX_DISABLE 0x08
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#define XE_OCR_ABORT 0x10
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#define XE_OCR_ONLINE 0x20
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#define XE_OCR_ACK_INTR 0x40
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#define XE_OCR_OFFLINE 0x80
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/*
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* Page 0x42 registers
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*/
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#define XE_SWC0 8 /* Software configuration register 0 */
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#define XE_SWC1 9 /* Software configuration register 1 */
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#define XE_BOC 10 /* Back-off configuration */
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/*
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* Page 0x44 registers
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*/
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#define XE_TDR0 8 /* Time domain reflectometry register 0 */
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#define XE_TDR1 9 /* Time domain reflectometry register 1 */
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#define XE_RXC0 10 /* Receive byte count low */
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#define XE_RXC1 11 /* Receive byte count high */
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/*
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* Page 0x45 registers
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*/
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#define XE_REV 15 /* Revision (read) */
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/*
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* Page 0x50 registers
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*/
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#define XE_IAR 8 /* Individual address register */
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/*
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* Pages 0x43, 0x46-0x4f and 0x51-0x5e apparently don't exist.
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* The remainder of 0x0-0x8 and 0x40-0x5f exist, but I have no
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* idea what's on most of them.
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*/
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/*
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* MII/PHY defines adapted from the xl driver. These need cleaning up a
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* little if we end up using them.
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*/
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#define XE_MII_CLK 0x01
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#define XE_MII_DIR 0x08
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#define XE_MII_WRD 0x02
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#define XE_MII_RDD 0x20
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#define XE_MII_STARTDELIM 0x01
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#define XE_MII_READOP 0x02
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#define XE_MII_WRITEOP 0x01
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#define XE_MII_TURNAROUND 0x02
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#define XE_MII_SET(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) | (x))
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#define XE_MII_CLR(x) XE_OUTB(XE_GPR2, (XE_INB(XE_GPR2) | 0x04) & ~(x))
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#define XL_PHY_GENCTL 0x00
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#define XL_PHY_GENSTS 0x01
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#define XL_PHY_VENID 0x02
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#define XL_PHY_DEVID 0x03
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#define XL_PHY_ANAR 0x04
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#define XL_PHY_LPAR 0x05
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#define XL_PHY_ANER 0x06
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#define PHY_ANAR_NEXTPAGE 0x8000
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#define PHY_ANAR_RSVD0 0x4000
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#define PHY_ANAR_TLRFLT 0x2000
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#define PHY_ANAR_RSVD1 0x1000
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#define PHY_ANAR_RSVD2 0x0800
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#define PHY_ANAR_RSVD3 0x0400
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#define PHY_ANAR_100BT4 0x0200
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#define PHY_ANAR_100BTXFULL 0x0100
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#define PHY_ANAR_100BTXHALF 0x0080
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#define PHY_ANAR_10BTFULL 0x0040
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#define PHY_ANAR_10BTHALF 0x0020
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#define PHY_ANAR_PROTO4 0x0010
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#define PHY_ANAR_PROTO3 0x0008
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#define PHY_ANAR_PROTO2 0x0004
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#define PHY_ANAR_PROTO1 0x0002
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#define PHY_ANAR_PROTO0 0x0001
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/*
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* PHY BMCR Basic Mode Control Register
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*/
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#define PHY_BMCR 0x00
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOPBK 0x4000
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#define PHY_BMCR_SPEEDSEL 0x2000
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#define PHY_BMCR_AUTONEGENBL 0x1000
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#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
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#define PHY_BMCR_ISOLATE 0x0400
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#define PHY_BMCR_AUTONEGRSTR 0x0200
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#define PHY_BMCR_DUPLEX 0x0100
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#define PHY_BMCR_COLLTEST 0x0080
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#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
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#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
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#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
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#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
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#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
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#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
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#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
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/*
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* PHY, BMSR Basic Mode Status Register
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*/
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#define PHY_BMSR 0x01
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#define PHY_BMSR_100BT4 0x8000
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#define PHY_BMSR_100BTXFULL 0x4000
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#define PHY_BMSR_100BTXHALF 0x2000
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#define PHY_BMSR_10BTFULL 0x1000
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#define PHY_BMSR_10BTHALF 0x0800
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#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
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#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
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#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
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#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
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#define PHY_BMSR_MFPRESUP 0x0040
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#define PHY_BMSR_AUTONEGCOMP 0x0020
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#define PHY_BMSR_REMFAULT 0x0010
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#define PHY_BMSR_CANAUTONEG 0x0008
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#define PHY_BMSR_LINKSTAT 0x0004
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#define PHY_BMSR_JABBER 0x0002
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#define PHY_BMSR_EXTENDED 0x0001
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#endif /* NXE > 0 */
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