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dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
126 lines
4.5 KiB
C
126 lines
4.5 KiB
C
/*-
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* Copyright (c) 2005, Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Machine dependent interfaces */
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#ifndef _DEV_HWPMC_PIV_H_
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#define _DEV_HWPMC_PIV_H_ 1
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/* Intel P4 PMCs */
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#define P4_NPMCS 18
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#define P4_NESCR 45
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#define P4_INVALID_PMC_INDEX -1
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#define P4_MAX_ESCR_PER_EVENT 2
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#define P4_MAX_PMC_PER_ESCR 3
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#define P4_CCCR_OVF (1 << 31)
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#define P4_CCCR_CASCADE (1 << 30)
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#define P4_CCCR_OVF_PMI_T1 (1 << 27)
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#define P4_CCCR_OVF_PMI_T0 (1 << 26)
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#define P4_CCCR_FORCE_OVF (1 << 25)
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#define P4_CCCR_EDGE (1 << 24)
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#define P4_CCCR_THRESHOLD_SHIFT 20
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#define P4_CCCR_THRESHOLD_MASK 0x00F00000
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#define P4_CCCR_TO_THRESHOLD(C) (((C) << P4_CCCR_THRESHOLD_SHIFT) & \
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P4_CCCR_THRESHOLD_MASK)
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#define P4_CCCR_COMPLEMENT (1 << 19)
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#define P4_CCCR_COMPARE (1 << 18)
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#define P4_CCCR_ACTIVE_THREAD_SHIFT 16
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#define P4_CCCR_ACTIVE_THREAD_MASK 0x00030000
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#define P4_CCCR_TO_ACTIVE_THREAD(T) (((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \
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P4_CCCR_ACTIVE_THREAD_MASK)
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#define P4_CCCR_ESCR_SELECT_SHIFT 13
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#define P4_CCCR_ESCR_SELECT_MASK 0x0000E000
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#define P4_CCCR_TO_ESCR_SELECT(E) (((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \
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P4_CCCR_ESCR_SELECT_MASK)
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#define P4_CCCR_ENABLE (1 << 12)
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#define P4_CCCR_VALID_BITS (P4_CCCR_OVF | P4_CCCR_CASCADE | \
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P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | \
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P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT | \
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P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE)
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#define P4_ESCR_EVENT_SELECT_SHIFT 25
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#define P4_ESCR_EVENT_SELECT_MASK 0x7E000000
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#define P4_ESCR_TO_EVENT_SELECT(E) (((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \
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P4_ESCR_EVENT_SELECT_MASK)
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#define P4_ESCR_EVENT_MASK_SHIFT 9
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#define P4_ESCR_EVENT_MASK_MASK 0x01FFFE00
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#define P4_ESCR_TO_EVENT_MASK(M) (((M) << P4_ESCR_EVENT_MASK_SHIFT) & \
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P4_ESCR_EVENT_MASK_MASK)
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#define P4_ESCR_TAG_VALUE_SHIFT 5
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#define P4_ESCR_TAG_VALUE_MASK 0x000001E0
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#define P4_ESCR_TO_TAG_VALUE(T) (((T) << P4_ESCR_TAG_VALUE_SHIFT) & \
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P4_ESCR_TAG_VALUE_MASK)
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#define P4_ESCR_TAG_ENABLE 0x00000010
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#define P4_ESCR_T0_OS 0x00000008
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#define P4_ESCR_T0_USR 0x00000004
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#define P4_ESCR_T1_OS 0x00000002
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#define P4_ESCR_T1_USR 0x00000001
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#define P4_ESCR_OS P4_ESCR_T0_OS
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#define P4_ESCR_USR P4_ESCR_T0_USR
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#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \
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P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \
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P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \
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P4_ESCR_T1_USR)
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#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */
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#define P4_PERFCTR_OVERFLOWED(PMC) ((rdpmc(PMC) & (1LL << 39)) == 0)
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#define P4_CCCR_MSR_FIRST 0x360 /* MSR_BPU_CCCR0 */
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#define P4_PERFCTR_MSR_FIRST 0x300 /* MSR_BPU_COUNTER0 */
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#define P4_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (1 - (V))
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#define P4_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (1 - (P))
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struct pmc_md_p4_op_pmcallocate {
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uint32_t pm_p4_cccrconfig;
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uint32_t pm_p4_escrconfig;
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};
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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struct pmc_md_p4_pmc {
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uint32_t pm_p4_cccrvalue;
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uint32_t pm_p4_escrvalue;
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uint32_t pm_p4_escr;
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uint32_t pm_p4_escrmsr;
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};
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/*
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* Prototypes
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*/
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int pmc_p4_initialize(struct pmc_mdep *_md, int _ncpus);
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void pmc_p4_finalize(struct pmc_mdep *md);
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_PIV_H_ */
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