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f1bc3750cf
While this won't be noticed by most users the time to zero the bss while using instruction tracing in the Arm FVP models (simulators) is noticeable. Reduce this time by using a store-pair instruction to double the size of memory we zero on each iteration of the loop. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D42733
148 lines
3.8 KiB
Plaintext
148 lines
3.8 KiB
Plaintext
OUTPUT_ARCH(aarch64)
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ENTRY(_start)
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SEARCH_DIR(/usr/lib);
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = text_start; /* This is set using --defsym= on the command line. */
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.vmm_vectors : { *(.vmm_vectors) }
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.text :
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{
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*(.text)
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*(.stub)
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning)
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*(.gnu.linkonce.t*)
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} =0x9090
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_etext = .;
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PROVIDE (etext = .);
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.fini : { *(.fini) } =0x9090
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.rodata : { *(.rodata*) *(.gnu.linkonce.r*) }
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.rodata1 : { *(.rodata1) }
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.gnu.version : { *(.gnu.version) }
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.gnu.version_d : { *(.gnu.version_d) }
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.gnu.version_r : { *(.gnu.version_r) }
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.note.gnu.build-id : {
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PROVIDE (__build_id_start = .);
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*(.note.gnu.build-id)
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PROVIDE (__build_id_end = .);
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}
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.rel.text :
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{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
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.rela.text :
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{ *(.rela.text) *(.rela.gnu.linkonce.t*) }
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.rel.data :
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{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
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.rela.data :
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{ *(.rela.data) *(.rela.gnu.linkonce.d*) }
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.rel.rodata :
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{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
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.rela.rodata :
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{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.init : { *(.rel.init) }
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.rela.init : { *(.rela.init) }
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.rel.fini : { *(.rel.fini) }
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.rela.fini : { *(.rela.fini) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) } =0x9090
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.plt : { *(.plt) }
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. = ALIGN(4);
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_extab_start = .;
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PROVIDE(extab_start = .);
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.ARM.extab : { *(.ARM.extab) }
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_extab.end = .;
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PROVIDE(extab_end = .);
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_exidx_start = .;
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PROVIDE(exidx_start = .);
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.ARM.exidx : { *(.ARM.exidx) }
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_exidx_end = .;
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PROVIDE(exidx_end = .);
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/* Adjust the address for the data segment. We want to adjust up to
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the same address within the page on the next page up. */
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. = ALIGN(0x1000) + (. & (0x1000 - 1)) ;
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.data :
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{
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*(.data)
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*(.gnu.linkonce.d*)
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}
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. = ALIGN(128);
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.data.read_frequently :
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{
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*(SORT_BY_ALIGNMENT(.data.read_frequently))
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}
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.data.read_mostly :
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{
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*(.data.read_mostly)
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}
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. = ALIGN(128);
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.data.exclusive_cache_line :
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{
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*(.data.exclusive_cache_line)
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}
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. = ALIGN(128);
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.data1 : { *(.data1) }
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. = ALIGN(32 / 8);
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_start_ctors = .;
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PROVIDE (start_ctors = .);
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.ctors :
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{
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*(.ctors)
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}
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_stop_ctors = .;
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PROVIDE (stop_ctors = .);
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.dtors :
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{
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*(.dtors)
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}
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.got : { *(.got.plt) *(.got) }
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.dynamic : { *(.dynamic) }
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/* We want the small data sections together, so single-instruction offsets
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can access them all, and initialized data all before uninitialized, so
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we can shorten the on-disk segment size. */
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. = ALIGN(8);
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.sdata : { *(.sdata) }
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_edata = .;
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PROVIDE (edata = .);
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. = ALIGN(16);
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__bss_start = .;
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.sbss : { *(.sbss) *(.scommon) }
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.bss :
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{
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*(.dynbss)
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*(.bss)
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*(COMMON)
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. = ALIGN(16);
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__bss_end = .;
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/* A section for the initial page table, it doesn't need to be in the
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kernel file, however unlike normal .bss entries should not be zeroed
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out as we use it before the .bss section is cleared. */
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*(.init_pagetable)
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}
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_end = . ;
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PROVIDE (end = .);
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/* Debug */
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INCLUDE debuginfo.ldscript
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.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
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/DISCARD/ : { *(.note.GNU-stack) }
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}
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