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8f1ca31497
- Special registers of IO-DATA device's RSA series are defined in ic/rsa.h (new file). Pointed out by: Bruce Evans <bde@zeta.org.au> Submitted by: Takahashi Yoshihiro <nyan@wyvern.cc.kogakuin.ac.jp>
129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/*-
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* Copyright (c) 1999 FreeBSD Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: $
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*/
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/*
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* RSA Mode Driver Data Sheet
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*
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* <<Register Map>>
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* Base + 0x00
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* Mode Select Register(Read/Write)
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* bit4=interrupt type(1: level, 0: edge)
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* bit3=Auto RTS-CTS Flow Control Enable
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* bit2=External FIFO Enable
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* bit1=Reserved(Default 0)Don't Change!!
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* bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
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*
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* Base + 0x01
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* Interrupt Enable Register(Read/Write)
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* bit4=Hardware Timer Interrupt Enable
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* bit3=Character Time-Out Interrupt Enable
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* bit2=Tx FIFO Empty Interrupt Enable
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* bit1=Tx FIFO Half Full Interrupt Enable
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* bit0=Rx FIFO Half Full Interrupt Enable
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*
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* Base + 0x02
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* Status Read Register(Read)
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* bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
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* bit6=Character Time Out Interrupt Status
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* bit5=Rx FIFO Full Flag(0: True, 1: False)
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* bit4=Rx FIFO Half Full Flag
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* bit3=Rx FIFO Empty Flag
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* bit2=Tx FIFO Full Flag
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* bit1=Tx FIFO Half Full Flag
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* bit0=Tx FIFO Empty Flag
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*
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* Base + 0x02
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* FIFO Reset Register(Write)
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* Reset Extrnal FIFO
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*
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* Base + 0x03
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* Timer Interval Value Set Register(Read/Write)
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* Range of n: 1-255
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* Interval Value: n * 0.2ms
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*
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* Base + 0x04
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* Timer Control Register(Read/Write)
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* bit0=Timer Enable
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*
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* Base + 0x08 - 0x0f
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* Same as UART 16550
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*
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* Special Regisgter in RSA Mode
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* UART Data Register(Base + 0x08)
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* Data transfer between Extrnal FIFO
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*
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* UART MCR(Base + 0x0c)
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* bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
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* bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
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*
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* <<Intrrupt and Intrrupt Reset>>
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* o Reciver Line Status(from UART16550)
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* Reset: Read LSR
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*
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* o Modem Status(from UART16550)
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* Reset: Read MSR
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*
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* o Rx FIFO Half Full(from Extrnal FIFO)
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* Reset: Read Rx FIFO under Hall Full
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*
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* o Character Time Out(from Extrnal FIFO)
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* Reset: Read Rx FIFO or SRR
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*
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* o Tx FIFO Empty(from Extrnal FIFO)
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* Reset: Write Tx FIFO or Read SRR
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*
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* o Tx FIFO Half Full(from Extrnal FIFO)
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* Reset: Write Tx FIFO until Hall Full or Read SRR
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*
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* o Hardware Timer(from Extrnal FIFO)
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* Reset: Disable Timer in TCR
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* Notes: If you want to use Timer for next intrrupt,
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* you must enable Timer in TCR
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*
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* <<Used Setting>>
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* Auto RTS-CTS: Enable or Disable
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* External FIFO: Enable
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* Swap 8bytes: Disable
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* Haredware Timer: Disable
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* interrupt type: edge
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* interrupt source:
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* Hareware Timer
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* Character Time Out
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* Tx FIFO Empty
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* Rx FIFO Half Full
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*
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*/
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/* I/O-DATA RSA Serise Exrension Register */
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#define rsa_msr 0 /* Mode Status Register (R/W) */
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#define rsa_ier 1 /* Interrupt Enable Register (R/W) */
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#define rsa_srr 2 /* Status Read Register (R) */
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#define rsa_frr 2 /* FIFO Reset Register (W) */
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#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
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#define rsa_tcr 4 /* Timer Control Register (W) */
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