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b50641ef9c
The old version only worked right when the time was read strictly more often than every 1/HZ seconds, but we only guarantee reading it every (1/HZ + epsilon) seconds. Part of rev.1.126-1.127 attempted to fix this but didn't succeed. Detect counter rollover using the heuristic from the old version of microtime() with additional complications for supporting calls from fast interrupt handlers. This works provided i8254 interrupts are not delayed by more than 1/(2*HZ) seconds. This needs more comments, and cleanups for the SMP case, and more testing of the SMP case before it is merged into RELENG_3. Tested by: jhay
225 lines
6.8 KiB
ArmAsm
225 lines
6.8 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: icu_vector.s,v 1.11 1999/04/28 01:04:13 luoqi Exp $
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*/
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/*
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* modified for PC98 by Kakefuda
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*/
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#endif
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) >> 3)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
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notl %eax ; \
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andl _ipending,%eax ; \
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jne 2f ; /* yes, maybe handle them */ \
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1: ; \
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MEXITCOUNT ; \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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cmpb $3,_intr_nesting_level ; /* is there enough stack? */ \
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jae 1b ; /* no, return */ \
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movl _cpl,%eax ; \
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/* XXX next line is probably unnecessary now. */ \
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movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \
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incb _intr_nesting_level ; /* ... really limit it ... */ \
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sti ; /* ... to do this as early as possible */ \
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MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
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popl %ecx ; /* ... original %ds ... */ \
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popl %edx ; \
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xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \
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pushal ; /* build fat frame (grrr) ... */ \
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pushl %ecx ; /* ... actually %ds ... */ \
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pushl %es ; \
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pushl %fs ; \
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movl $KDSEL,%eax ; \
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movl %ax,%es ; \
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movl %ax,%fs ; \
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movl (3+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \
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movl %ecx,(3+6)*4(%esp) ; /* ... to fat frame ... */ \
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movl (3+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \
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pushl %eax ; \
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subl $4,%esp ; /* junk for unit number */ \
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MEXITCOUNT ; \
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jmp _doreti
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#define INTR(irq_num, vec_name, icu, enable_icus, reg, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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pushl %fs ; \
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movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
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movl %ax,%ds ; /* ... early for obsolete reasons */ \
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movl %ax,%es ; \
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movl %ax,%fs ; \
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maybe_extra_ipending ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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enable_icus ; \
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movl _cpl,%eax ; \
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testb $IRQ_BIT(irq_num),%reg ; \
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jne 2f ; \
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incb _intr_nesting_level ; \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX late to avoid double count */ \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; \
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pushl %eax ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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orl _intr_mask + (irq_num) * 4,%eax ; \
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movl %eax,_cpl ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; /* must unmask _imen and icu atomically */ \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* _doreti, but it's probably better to use less cache. */ \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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/* XXX skip mcounting here to avoid double count */ \
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
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#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al, CLKINTR_PENDING)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al,)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al,)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al,)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al,)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al,)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al,)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al,)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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MCOUNT_LABEL(eintr)
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.data
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.globl _ihandlers
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_ihandlers: /* addresses of interrupt handlers */
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/* actually resumption addresses for HWI's */
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.long Xresume0, Xresume1, Xresume2, Xresume3
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.long Xresume4, Xresume5, Xresume6, Xresume7
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.long Xresume8, Xresume9, Xresume10, Xresume11
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.long Xresume12, Xresume13, Xresume14, Xresume15
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.long _swi_null, swi_net, _swi_null, _swi_null
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.long _swi_vm, _swi_null, _swi_null, _swi_null
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.long _swi_null, _swi_null, _swi_null, _swi_null
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.long _swi_null, _swi_null, _softclock, swi_ast
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imasks: /* masks for interrupt handlers */
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.space NHWI*4 /* padding; HWI masks are elsewhere */
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.long SWI_TTY_MASK, SWI_NET_MASK, SWI_CAMNET_MASK, SWI_CAMBIO_MASK
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.long SWI_VM_MASK, 0, 0, 0
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.long 0, 0, 0, 0
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.long 0, 0, SWI_CLOCK_MASK, SWI_AST_MASK
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.text
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