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141 lines
4.0 KiB
C
141 lines
4.0 KiB
C
/*-
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* Copyright (c) 1998 Nicolas Souchu, Marc Bouget
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* Copyright (c) 2004 Joerg Wunsch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define IO_PCFSIZE 2
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#define TIMEOUT 9999 /* XXX */
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/* Status bits of S1 register (read only) */
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#define nBB 0x01 /* busy when low set/reset by STOP/START*/
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#define LAB 0x02 /* lost arbitration bit in multi-master mode */
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#define AAS 0x04 /* addressed as slave */
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#define LRB 0x08 /* last received byte when not AAS */
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#define AD0 0x08 /* general call received when AAS */
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#define BER 0x10 /* bus error, misplaced START or STOP */
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#define STS 0x20 /* STOP detected in slave receiver mode */
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#define PIN 0x80 /* pending interrupt not (r/w) */
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/* Control bits of S1 register (write only) */
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#define ACK 0x01
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#define STO 0x02
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#define STA 0x04
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#define ENI 0x08
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#define ES2 0x10
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#define ES1 0x20
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#define ESO 0x40
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#define BUFSIZE 2048
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#define SLAVE_TRANSMITTER 0x1
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#define SLAVE_RECEIVER 0x2
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#define PCF_DEFAULT_ADDR 0xaa
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struct pcf_softc {
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u_char pcf_addr; /* interface I2C address */
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int pcf_flags; /* IIC_POLLED? */
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int pcf_slave_mode; /* receiver or transmitter */
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int pcf_started; /* 1 if start condition sent */
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device_t iicbus; /* the corresponding iicbus */
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/* Resource handling stuff. */
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struct resource *res_ioport;
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int rid_ioport;
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bus_space_tag_t bt_ioport;
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bus_space_handle_t bh_ioport;
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struct resource *res_irq;
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int rid_irq;
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void *intr_cookie;
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};
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#define DEVTOSOFTC(dev) ((struct pcf_softc *)device_get_softc(dev))
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/*
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* PCF8584 datasheet : when operate at 8 MHz or more, a minimun time of
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* 6 clocks cycles must be left between two consecutives access
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*/
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#define pcf_nops() DELAY(10)
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#define dummy_read(sc) pcf_get_S0(sc)
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#define dummy_write(sc) pcf_set_S0(sc, 0)
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/*
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* Specific register access to PCF8584
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*/
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static __inline void
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pcf_set_S0(struct pcf_softc *sc, int data)
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{
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bus_space_write_1(sc->bt_ioport, sc->bh_ioport, 0, data);
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pcf_nops();
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}
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static __inline void
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pcf_set_S1(struct pcf_softc *sc, int data)
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{
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bus_space_write_1(sc->bt_ioport, sc->bh_ioport, 1, data);
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pcf_nops();
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}
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static __inline char
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pcf_get_S0(struct pcf_softc *sc)
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{
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char data;
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data = bus_space_read_1(sc->bt_ioport, sc->bh_ioport, 0);
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pcf_nops();
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return (data);
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}
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static __inline char
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pcf_get_S1(struct pcf_softc *sc)
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{
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char data;
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data = bus_space_read_1(sc->bt_ioport, sc->bh_ioport, 1);
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pcf_nops();
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return (data);
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}
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extern int pcf_repeated_start(device_t, u_char, int);
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extern int pcf_start(device_t, u_char, int);
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extern int pcf_stop(device_t);
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extern int pcf_write(device_t, char *, int, int *, int);
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extern int pcf_read(device_t, char *, int, int *, int, int);
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extern int pcf_rst_card(device_t, u_char, u_char, u_char *);
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extern driver_intr_t pcf_intr;
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#define PCF_MODVER 1
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#define PCF_MINVER 1
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#define PCF_MAXVER 1
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#define PCF_PREFVER PCF_MODVER
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