mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-21 11:13:30 +00:00
491 lines
14 KiB
Plaintext
491 lines
14 KiB
Plaintext
@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
|
|
@c Free Software Foundation, Inc.
|
|
@c This is part of the GAS manual.
|
|
@c For copying conditions, see the file as.texinfo.
|
|
|
|
@ifset GENERIC
|
|
@page
|
|
@node ARM-Dependent
|
|
@chapter ARM Dependent Features
|
|
@end ifset
|
|
|
|
@ifclear GENERIC
|
|
@node Machine Dependencies
|
|
@chapter ARM Dependent Features
|
|
@end ifclear
|
|
|
|
@cindex ARM support
|
|
@cindex Thumb support
|
|
@menu
|
|
* ARM Options:: Options
|
|
* ARM Syntax:: Syntax
|
|
* ARM Floating Point:: Floating Point
|
|
* ARM Directives:: ARM Machine Directives
|
|
* ARM Opcodes:: Opcodes
|
|
* ARM Mapping Symbols:: Mapping Symbols
|
|
@end menu
|
|
|
|
@node ARM Options
|
|
@section Options
|
|
@cindex ARM options (none)
|
|
@cindex options for ARM (none)
|
|
|
|
@table @code
|
|
|
|
@cindex @code{-mcpu=} command line option, ARM
|
|
@item -mcpu=@var{processor}[+@var{extension}@dots{}]
|
|
This option specifies the target processor. The assembler will issue an
|
|
error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target processor. The following processor names are
|
|
recognized:
|
|
@code{arm1},
|
|
@code{arm2},
|
|
@code{arm250},
|
|
@code{arm3},
|
|
@code{arm6},
|
|
@code{arm60},
|
|
@code{arm600},
|
|
@code{arm610},
|
|
@code{arm620},
|
|
@code{arm7},
|
|
@code{arm7m},
|
|
@code{arm7d},
|
|
@code{arm7dm},
|
|
@code{arm7di},
|
|
@code{arm7dmi},
|
|
@code{arm70},
|
|
@code{arm700},
|
|
@code{arm700i},
|
|
@code{arm710},
|
|
@code{arm710t},
|
|
@code{arm720},
|
|
@code{arm720t},
|
|
@code{arm740t},
|
|
@code{arm710c},
|
|
@code{arm7100},
|
|
@code{arm7500},
|
|
@code{arm7500fe},
|
|
@code{arm7t},
|
|
@code{arm7tdmi},
|
|
@code{arm8},
|
|
@code{arm810},
|
|
@code{strongarm},
|
|
@code{strongarm1},
|
|
@code{strongarm110},
|
|
@code{strongarm1100},
|
|
@code{strongarm1110},
|
|
@code{arm9},
|
|
@code{arm920},
|
|
@code{arm920t},
|
|
@code{arm922t},
|
|
@code{arm940t},
|
|
@code{arm9tdmi},
|
|
@code{arm9e},
|
|
@code{arm926e},
|
|
@code{arm926ejs},
|
|
@code{arm946e-r0},
|
|
@code{arm946e},
|
|
@code{arm966e-r0},
|
|
@code{arm966e},
|
|
@code{arm10t},
|
|
@code{arm10e},
|
|
@code{arm1020},
|
|
@code{arm1020t},
|
|
@code{arm1020e},
|
|
@code{arm1026ejs},
|
|
@code{arm1136js},
|
|
@code{arm1136jfs},
|
|
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
|
|
@code{i80200} (Intel XScale processor)
|
|
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
|
|
and
|
|
@code{xscale}.
|
|
The special name @code{all} may be used to allow the
|
|
assembler to accept instructions valid for any ARM processor.
|
|
|
|
In addition to the basic instruction set, the assembler can be told to
|
|
accept various extension mnemonics that extend the processor using the
|
|
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
|
|
is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
|
|
are currently supported:
|
|
@code{+maverick}
|
|
@code{+iwmmxt}
|
|
and
|
|
@code{+xscale}.
|
|
|
|
@cindex @code{-march=} command line option, ARM
|
|
@item -march=@var{architecture}[+@var{extension}@dots{}]
|
|
This option specifies the target architecture. The assembler will issue
|
|
an error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target architecture. The following architecture
|
|
names are recognized:
|
|
@code{armv1},
|
|
@code{armv2},
|
|
@code{armv2a},
|
|
@code{armv2s},
|
|
@code{armv3},
|
|
@code{armv3m},
|
|
@code{armv4},
|
|
@code{armv4xm},
|
|
@code{armv4t},
|
|
@code{armv4txm},
|
|
@code{armv5},
|
|
@code{armv5t},
|
|
@code{armv5txm},
|
|
@code{armv5te},
|
|
@code{armv5texp},
|
|
@code{armv6},
|
|
@code{armv6j},
|
|
@code{iwmmxt}
|
|
and
|
|
@code{xscale}.
|
|
If both @code{-mcpu} and
|
|
@code{-march} are specified, the assembler will use
|
|
the setting for @code{-mcpu}.
|
|
|
|
The architecture option can be extended with the same instruction set
|
|
extension options as the @code{-mcpu} option.
|
|
|
|
@cindex @code{-mfpu=} command line option, ARM
|
|
@item -mfpu=@var{floating-point-format}
|
|
|
|
This option specifies the floating point format to assemble for. The
|
|
assembler will issue an error message if an attempt is made to assemble
|
|
an instruction which will not execute on the target floating point unit.
|
|
The following format options are recognized:
|
|
@code{softfpa},
|
|
@code{fpe},
|
|
@code{fpe2},
|
|
@code{fpe3},
|
|
@code{fpa},
|
|
@code{fpa10},
|
|
@code{fpa11},
|
|
@code{arm7500fe},
|
|
@code{softvfp},
|
|
@code{softvfp+vfp},
|
|
@code{vfp},
|
|
@code{vfp10},
|
|
@code{vfp10-r0},
|
|
@code{vfp9},
|
|
@code{vfpxd},
|
|
@code{arm1020t},
|
|
@code{arm1020e},
|
|
@code{arm1136jfs}
|
|
and
|
|
@code{maverick}.
|
|
|
|
In addition to determining which instructions are assembled, this option
|
|
also affects the way in which the @code{.double} assembler directive behaves
|
|
when assembling little-endian code.
|
|
|
|
The default is dependent on the processor selected. For Architecture 5 or
|
|
later, the default is to assembler for VFP instructions; for earlier
|
|
architectures the default is to assemble for FPA instructions.
|
|
|
|
@cindex @code{-mthumb} command line option, ARM
|
|
@item -mthumb
|
|
This option specifies that the assembler should start assembling Thumb
|
|
instructions; that is, it should behave as though the file starts with a
|
|
@code{.code 16} directive.
|
|
|
|
@cindex @code{-mthumb-interwork} command line option, ARM
|
|
@item -mthumb-interwork
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as supporting interworking.
|
|
|
|
@cindex @code{-mapcs} command line option, ARM
|
|
@item -mapcs @code{[26|32]}
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as supporting the indicated version of the Arm Procedure.
|
|
Calling Standard.
|
|
|
|
@cindex @code{-matpcs} command line option, ARM
|
|
@item -matpcs
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
|
|
enabled this option will cause the assembler to create an empty
|
|
debugging section in the object file called .arm.atpcs. Debuggers can
|
|
use this to determine the ABI being used by.
|
|
|
|
@cindex @code{-mapcs-float} command line option, ARM
|
|
@item -mapcs-float
|
|
This indicates the floating point variant of the APCS should be
|
|
used. In this variant floating point arguments are passed in FP
|
|
registers rather than integer registers.
|
|
|
|
@cindex @code{-mapcs-reentrant} command line option, ARM
|
|
@item -mapcs-reentrant
|
|
This indicates that the reentrant variant of the APCS should be used.
|
|
This variant supports position independent code.
|
|
|
|
@cindex @code{-mfloat-abi=} command line option, ARM
|
|
@item -mfloat-abi=@var{abi}
|
|
This option specifies that the output generated by the assembler should be
|
|
marked as using specified floating point ABI.
|
|
The following values are recognized:
|
|
@code{soft},
|
|
@code{softfp}
|
|
and
|
|
@code{hard}.
|
|
|
|
@cindex @code{-EB} command line option, ARM
|
|
@item -EB
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a big-endian processor.
|
|
|
|
@cindex @code{-EL} command line option, ARM
|
|
@item -EL
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a little-endian processor.
|
|
|
|
@cindex @code{-k} command line option, ARM
|
|
@cindex PIC code generation for ARM
|
|
@item -k
|
|
This option specifies that the output of the assembler should be marked
|
|
as position-independent code (PIC).
|
|
|
|
@cindex @code{-moabi} command line option, ARM
|
|
@item -moabi
|
|
This indicates that the code should be assembled using the old ARM ELF
|
|
conventions, based on a beta release release of the ARM-ELF
|
|
specifications, rather than the default conventions which are based on
|
|
the final release of the ARM-ELF specifications.
|
|
|
|
@end table
|
|
|
|
|
|
@node ARM Syntax
|
|
@section Syntax
|
|
@menu
|
|
* ARM-Chars:: Special Characters
|
|
* ARM-Regs:: Register Names
|
|
@end menu
|
|
|
|
@node ARM-Chars
|
|
@subsection Special Characters
|
|
|
|
@cindex line comment character, ARM
|
|
@cindex ARM line comment character
|
|
The presence of a @samp{@@} on a line indicates the start of a comment
|
|
that extends to the end of the current line. If a @samp{#} appears as
|
|
the first character of a line, the whole line is treated as a comment.
|
|
|
|
@cindex line separator, ARM
|
|
@cindex statement separator, ARM
|
|
@cindex ARM line separator
|
|
The @samp{;} character can be used instead of a newline to separate
|
|
statements.
|
|
|
|
@cindex immediate character, ARM
|
|
@cindex ARM immediate character
|
|
Either @samp{#} or @samp{$} can be used to indicate immediate operands.
|
|
|
|
@cindex identifiers, ARM
|
|
@cindex ARM identifiers
|
|
*TODO* Explain about /data modifier on symbols.
|
|
|
|
@node ARM-Regs
|
|
@subsection Register Names
|
|
|
|
@cindex ARM register names
|
|
@cindex register names, ARM
|
|
*TODO* Explain about ARM register naming, and the predefined names.
|
|
|
|
@node ARM Floating Point
|
|
@section Floating Point
|
|
|
|
@cindex floating point, ARM (@sc{ieee})
|
|
@cindex ARM floating point (@sc{ieee})
|
|
The ARM family uses @sc{ieee} floating-point numbers.
|
|
|
|
|
|
|
|
@node ARM Directives
|
|
@section ARM Machine Directives
|
|
|
|
@cindex machine directives, ARM
|
|
@cindex ARM machine directives
|
|
@table @code
|
|
|
|
@cindex @code{align} directive, ARM
|
|
@item .align @var{expression} [, @var{expression}]
|
|
This is the generic @var{.align} directive. For the ARM however if the
|
|
first argument is zero (ie no alignment is needed) the assembler will
|
|
behave as if the argument had been 2 (ie pad to the next four byte
|
|
boundary). This is for compatibility with ARM's own assembler.
|
|
|
|
@cindex @code{req} directive, ARM
|
|
@item @var{name} .req @var{register name}
|
|
This creates an alias for @var{register name} called @var{name}. For
|
|
example:
|
|
|
|
@smallexample
|
|
foo .req r0
|
|
@end smallexample
|
|
|
|
@cindex @code{unreq} directive, ARM
|
|
@item .unreq @var{alias-name}
|
|
This undefines a register alias which was previously defined using the
|
|
@code{req} directive. For example:
|
|
|
|
@smallexample
|
|
foo .req r0
|
|
.unreq foo
|
|
@end smallexample
|
|
|
|
An error occurs if the name is undefined. Note - this pseudo op can
|
|
be used to delete builtin in register name aliases (eg 'r0'). This
|
|
should only be done if it is really necessary.
|
|
|
|
@cindex @code{code} directive, ARM
|
|
@item .code @code{[16|32]}
|
|
This directive selects the instruction set being generated. The value 16
|
|
selects Thumb, with the value 32 selecting ARM.
|
|
|
|
@cindex @code{thumb} directive, ARM
|
|
@item .thumb
|
|
This performs the same action as @var{.code 16}.
|
|
|
|
@cindex @code{arm} directive, ARM
|
|
@item .arm
|
|
This performs the same action as @var{.code 32}.
|
|
|
|
@cindex @code{force_thumb} directive, ARM
|
|
@item .force_thumb
|
|
This directive forces the selection of Thumb instructions, even if the
|
|
target processor does not support those instructions
|
|
|
|
@cindex @code{thumb_func} directive, ARM
|
|
@item .thumb_func
|
|
This directive specifies that the following symbol is the name of a
|
|
Thumb encoded function. This information is necessary in order to allow
|
|
the assembler and linker to generate correct code for interworking
|
|
between Arm and Thumb instructions and should be used even if
|
|
interworking is not going to be performed. The presence of this
|
|
directive also implies @code{.thumb}
|
|
|
|
@cindex @code{thumb_set} directive, ARM
|
|
@item .thumb_set
|
|
This performs the equivalent of a @code{.set} directive in that it
|
|
creates a symbol which is an alias for another symbol (possibly not yet
|
|
defined). This directive also has the added property in that it marks
|
|
the aliased symbol as being a thumb function entry point, in the same
|
|
way that the @code{.thumb_func} directive does.
|
|
|
|
@cindex @code{.ltorg} directive, ARM
|
|
@item .ltorg
|
|
This directive causes the current contents of the literal pool to be
|
|
dumped into the current section (which is assumed to be the .text
|
|
section) at the current location (aligned to a word boundary).
|
|
@code{GAS} maintains a separate literal pool for each section and each
|
|
sub-section. The @code{.ltorg} directive will only affect the literal
|
|
pool of the current section and sub-section. At the end of assembly
|
|
all remaining, un-empty literal pools will automatically be dumped.
|
|
|
|
Note - older versions of @code{GAS} would dump the current literal
|
|
pool any time a section change occurred. This is no longer done, since
|
|
it prevents accurate control of the placement of literal pools.
|
|
|
|
@cindex @code{.pool} directive, ARM
|
|
@item .pool
|
|
This is a synonym for .ltorg.
|
|
|
|
@end table
|
|
|
|
@node ARM Opcodes
|
|
@section Opcodes
|
|
|
|
@cindex ARM opcodes
|
|
@cindex opcodes for ARM
|
|
@code{@value{AS}} implements all the standard ARM opcodes. It also
|
|
implements several pseudo opcodes, including several synthetic load
|
|
instructions.
|
|
|
|
@table @code
|
|
|
|
@cindex @code{NOP} pseudo op, ARM
|
|
@item NOP
|
|
@smallexample
|
|
nop
|
|
@end smallexample
|
|
|
|
This pseudo op will always evaluate to a legal ARM instruction that does
|
|
nothing. Currently it will evaluate to MOV r0, r0.
|
|
|
|
@cindex @code{LDR reg,=<label>} pseudo op, ARM
|
|
@item LDR
|
|
@smallexample
|
|
ldr <register> , = <expression>
|
|
@end smallexample
|
|
|
|
If expression evaluates to a numeric constant then a MOV or MVN
|
|
instruction will be used in place of the LDR instruction, if the
|
|
constant can be generated by either of these instructions. Otherwise
|
|
the constant will be placed into the nearest literal pool (if it not
|
|
already there) and a PC relative LDR instruction will be generated.
|
|
|
|
@cindex @code{ADR reg,<label>} pseudo op, ARM
|
|
@item ADR
|
|
@smallexample
|
|
adr <register> <label>
|
|
@end smallexample
|
|
|
|
This instruction will load the address of @var{label} into the indicated
|
|
register. The instruction will evaluate to a PC relative ADD or SUB
|
|
instruction depending upon where the label is located. If the label is
|
|
out of range, or if it is not defined in the same file (and section) as
|
|
the ADR instruction, then an error will be generated. This instruction
|
|
will not make use of the literal pool.
|
|
|
|
@cindex @code{ADRL reg,<label>} pseudo op, ARM
|
|
@item ADRL
|
|
@smallexample
|
|
adrl <register> <label>
|
|
@end smallexample
|
|
|
|
This instruction will load the address of @var{label} into the indicated
|
|
register. The instruction will evaluate to one or two PC relative ADD
|
|
or SUB instructions depending upon where the label is located. If a
|
|
second instruction is not needed a NOP instruction will be generated in
|
|
its place, so that this instruction is always 8 bytes long.
|
|
|
|
If the label is out of range, or if it is not defined in the same file
|
|
(and section) as the ADRL instruction, then an error will be generated.
|
|
This instruction will not make use of the literal pool.
|
|
|
|
@end table
|
|
|
|
For information on the ARM or Thumb instruction sets, see @cite{ARM
|
|
Software Development Toolkit Reference Manual}, Advanced RISC Machines
|
|
Ltd.
|
|
|
|
@node ARM Mapping Symbols
|
|
@section Mapping Symbols
|
|
|
|
The ARM ELF specification requires that special symbols be inserted
|
|
into object files to mark certain features:
|
|
|
|
@table @code
|
|
|
|
@cindex @code{$a}
|
|
@item $a
|
|
At the start of a region of code containing ARM instructions.
|
|
|
|
@cindex @code{$t}
|
|
@item $t
|
|
At the start of a region of code containing THUMB instructions.
|
|
|
|
@cindex @code{$d}
|
|
@item $d
|
|
At the start of a region of data.
|
|
|
|
@end table
|
|
|
|
The assembler will automatically insert these symbols for you - there
|
|
is no need to code them yourself. Support for tagging symbols ($b,
|
|
$f, $p and $m) which is also mentioned in the current ARM ELF
|
|
specification is not implemented. This is because they have been
|
|
dropped from the new EABI and so tools cannot rely upon their
|
|
presence.
|
|
|