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0db7e66cdc
Files:
dev/cardbus/cardbus.c
dev/cardbus/cardbusreg.h
dev/cardbus/cardbusvar.h
dev/cardbus/cardbus_cis.c
dev/cardbus/cardbus_cis.h
dev/pccbb/pccbb.c
dev/pccbb/pccbbreg.h
dev/pccbb/pccbbvar.h
dev/pccbb/pccbb_if.m
This should support:
- cardbus controllers:
* TI 113X
* TI 12XX
* TI 14XX
* Ricoh 47X
* Ricoh 46X
* ToPIC 95
* ToPIC 97
* ToPIC 100
* Cirrus Logic CLPD683x
- cardbus cards
* 3c575BT
* 3c575CT
* Xircom X3201 (includes IBM, Xircom and, Intel cards)
[ 3com support already in kernel, Xircom will be committed real soon now]
This doesn't work with 16bit pccards under NEWCARD.
Enable in your config by having "device pccbb" and "device cardbus".
(A "device pccard" will attach a pccard bus, but it means you system have
a high chance of panicing when a 16bit card is inserted)
It should be fairly simple to make a driver attach to cardbus under
NEWCARD -- simply add an entry for attaching to cardbus on a new
DRIVER_MODULE and add new device IDs as necessary. You should also make
sure the card can be detached nicely without the interrupt routine doing
something weird, like going into an infinite loop. Usually that should
entail adding an additional check when a pci register or the bus space is
read to check if it equals 0xffffffff.
Any problems, please let me know.
Reviewed by: imp
189 lines
8.0 KiB
C
189 lines
8.0 KiB
C
/*
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* Copyright (c) 2000,2001 Jonathan Chen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Register definitions for PCI to Cardbus Bridge chips
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*/
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/* PCI header registers */
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#define PCCBBR_SOCKBASE 0x10 /* len=4 */
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#define PCCBBR_MEMBASE0 0x1c /* len=4 */
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#define PCCBBR_MEMLIMIT0 0x20 /* len=4 */
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#define PCCBBR_MEMBASE1 0x24 /* len=4 */
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#define PCCBBR_MEMLIMIT1 0x28 /* len=4 */
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#define PCCBBR_IOBASE0 0x2c /* len=4 */
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#define PCCBBR_IOLIMIT0 0x30 /* len=4 */
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#define PCCBBR_IOBASE1 0x34 /* len=4 */
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#define PCCBBR_IOLIMIT1 0x38 /* len=4 */
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#define PCCBB_MEMALIGN 4096
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#define PCCBB_IOALIGN 4
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#define PCCBBR_INTRLINE 0x3c /* len=1 */
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#define PCCBBR_INTRPIN 0x3d /* len=1 */
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#define PCCBBR_BRIDGECTRL 0x3e /* len=2 */
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# define PCCBBM_BRIDGECTRL_MASTER_ABORT 0x0020
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# define PCCBBM_BRIDGECTRL_RESET 0x0040
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# define PCCBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080
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# define PCCBBM_BRIDGECTRL_PREFETCH_0 0x0100
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# define PCCBBM_BRIDGECTRL_PREFETCH_1 0x0200
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# define PCCBBM_BRIDGECTRL_WRITE_POST_EN 0x0400
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/* additional bit for RF5C46[567] */
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# define PCCBBM_BRIDGECTRL_RL_3E0_EN 0x0800
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# define PCCBBM_BRIDGECTRL_RL_3E2_EN 0x1000
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#define PCCBBR_LEGACY 0x44 /* len=4 */
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#define PCCBBR_CBCTRL 0x91 /* len=1 */
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/* bits for TI 113X */
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# define PCCBBM_CBCTRL_113X_RI_EN 0x80
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# define PCCBBM_CBCTRL_113X_ZV_EN 0x40
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# define PCCBBM_CBCTRL_113X_PCI_IRQ_EN 0x20
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# define PCCBBM_CBCTRL_113X_PCI_INTR 0x10
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# define PCCBBM_CBCTRL_113X_PCI_CSC 0x08
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# define PCCBBM_CBCTRL_113X_PCI_CSC_D 0x04
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# define PCCBBM_CBCTRL_113X_SPEAKER_EN 0x02
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# define PCCBBM_CBCTRL_113X_INTR_DET 0x01
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/* bits for TI 12XX */
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# define PCCBBM_CBCTRL_12XX_RI_EN 0x80
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# define PCCBBM_CBCTRL_12XX_ZV_EN 0x40
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# define PCCBBM_CBCTRL_12XX_AUD2MUX 0x04
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# define PCCBBM_CBCTRL_12XX_SPEAKER_EN 0x02
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# define PCCBBM_CBCTRL_12XX_INTR_DET 0x01
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#define PCCBBR_DEVCTRL 0x92 /* len=1 */
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# define PCCBBM_DEVCTRL_INT_SERIAL 0x04
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# define PCCBBM_DEVCTRL_INT_PCI 0x02
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#define PCCBBR_TOPIC_SOCKETCTRL 0x90
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# define PCCBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
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#define PCCBBR_TOPIC_SLOTCTRL 0xa0
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# define PCCBBM_TOPIC_SLOTCTRL_SLOTON 0x00000080
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# define PCCBBM_TOPIC_SLOTCTRL_SLOTEN 0x00000040
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# define PCCBBM_TOPIC_SLOTCTRL_ID_LOCK 0x00000020
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# define PCCBBM_TOPIC_SLOTCTRL_ID_WP 0x00000010
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# define PCCBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0000000c
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# define PCCBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2
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# define PCCBBM_TOPIC_SLOTCTRL_OSF_MASK 0x00000003
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# define PCCBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0
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# define PCCBBM_TOPIC_SLOTCTRL_INTB 0x00002000
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# define PCCBBM_TOPIC_SLOTCTRL_INTA 0x00001000
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# define PCCBBM_TOPIC_SLOTCTRL_INT_MASK 0x00003000
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# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_MASK 0x00000c00
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# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */
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# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_1 0x00000400 /* PCI Clock */
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# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_0 0x00000000 /* no clock */
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# define PCCBBM_TOPIC_SLOTCTRL_CARDBUS 0x80000000
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# define PCCBBM_TOPIC_SLOTCTRL_VS1 0x04000000
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# define PCCBBM_TOPIC_SLOTCTRL_VS2 0x02000000
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# define PCCBBM_TOPIC_SLOTCTRL_SWDETECT 0x01000000
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/* Socket definitions */
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#define PCCBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */
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#define PCCBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */
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#define PCCBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */
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#define PCCBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */
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#define PCCBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */
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#define PCCBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */
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#define PCCBB_SOCKET_MASK_CD 0x06 /* Card Detect */
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#define PCCBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */
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#define PCCBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */
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#define PCCBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */
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#define PCCBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */
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#define PCCBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */
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#define PCCBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */
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#define PCCBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */
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#define PCCBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */
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#define PCCBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */
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#define PCCBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */
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#define PCCBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */
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#define PCCBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */
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#define PCCBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
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#define PCCBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
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#define PCCBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
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#define PCCBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
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#define PCCBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
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#define PCCBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
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#define PCCBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
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#define PCCBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
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#define PCCBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
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#define PCCBB_SOCKET_CTRL_VPPMASK 0x07
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#define PCCBB_SOCKET_CTRL_VPP_OFF 0x00
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#define PCCBB_SOCKET_CTRL_VPP_12V 0x01
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#define PCCBB_SOCKET_CTRL_VPP_5V 0x02
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#define PCCBB_SOCKET_CTRL_VPP_3V 0x03
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#define PCCBB_SOCKET_CTRL_VPP_XV 0x04
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#define PCCBB_SOCKET_CTRL_VPP_YV 0x05
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#define PCCBB_SOCKET_CTRL_VCCMASK 0x70
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#define PCCBB_SOCKET_CTRL_VCC_OFF 0x00
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#define PCCBB_SOCKET_CTRL_VCC_5V 0x20
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#define PCCBB_SOCKET_CTRL_VCC_3V 0x30
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#define PCCBB_SOCKET_CTRL_VCC_XV 0x40
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#define PCCBB_SOCKET_CTRL_VCC_YV 0x50
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#define PCCBB_SOCKET_CTRL_STOPCLK 0x80
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/* Vendor/Device IDs */
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#define PCI_DEVICE_ID_PCIC_OZ6729 0x67291217ul
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#define PCI_DEVICE_ID_PCIC_OZ6730 0x673A1217ul
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#define PCI_DEVICE_ID_PCIC_CLPD6729 0x11001013ul
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#define PCI_DEVICE_ID_PCIC_CLPD6832 0x11101013ul
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#define PCI_DEVICE_ID_PCIC_CLPD6833 0x11131013ul
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#define PCI_DEVICE_ID_PCIC_TI1130 0xac12104cul
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#define PCI_DEVICE_ID_PCIC_TI1131 0xac15104cul
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#define PCI_DEVICE_ID_PCIC_TI1211 0xac1e104cul
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#define PCI_DEVICE_ID_PCIC_TI1220 0xac17104cul
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#define PCI_DEVICE_ID_PCIC_TI1221 0xac19104cul
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#define PCI_DEVICE_ID_PCIC_TI1225 0xac1c104cul
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#define PCI_DEVICE_ID_PCIC_TI1250 0xac16104cul
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#define PCI_DEVICE_ID_PCIC_TI1251 0xac1d104cul
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#define PCI_DEVICE_ID_PCIC_TI1251B 0xac1f104cul
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#define PCI_DEVICE_ID_PCIC_TI1410 0xac50104cul
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#define PCI_DEVICE_ID_PCIC_TI1420 0xac51104cul
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#define PCI_DEVICE_ID_PCIC_TI1450 0xac1b104cul
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#define PCI_DEVICE_ID_PCIC_TI1451 0xac52104cul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x06031179ul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC95B 0x060a1179ul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f1179ul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x06171179ul
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#define PCI_DEVICE_ID_RICOH_RL5C465 0x04651180ul
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#define PCI_DEVICE_ID_RICOH_RL5C466 0x04661180ul
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#define PCI_DEVICE_ID_RICOH_RL5C475 0x04751180ul
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#define PCI_DEVICE_ID_RICOH_RL5C476 0x04761180ul
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#define PCI_DEVICE_ID_RICOH_RL5C477 0x04771180ul
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#define PCI_DEVICE_ID_RICOH_RL5C478 0x04781180ul
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