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a541c47546
The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
202 lines
4.5 KiB
ArmAsm
202 lines
4.5 KiB
ArmAsm
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/cpucontrol.h>
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#define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \
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XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4)
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#include "assym.s"
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.text
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.set noat
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.set noreorder
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.set mips64
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#define MFCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x18))
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#define MTCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x19))
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/*
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* We need to do this to really flush the dcache before splitting it
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*/
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.macro flush_l1_dcache
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.set push
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.set noreorder
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li $8, LSU_DEBUG_DATA0 /* use register number to handle */
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li $9, LSU_DEBUG_ADDR /* different ABIs */
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li t2, 0
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li t3, 0x200
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1:
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sll v0, t2, 5
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MTCR(0, 8)
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ori v1, v0, 0x3
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MTCR(3, 9)
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2:
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MFCR(3, 9)
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andi v1, 0x1
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bnez v1, 2b
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nop
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MTCR(0, 8)
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ori v1, v0, 0x7
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MTCR(3, 9)
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3:
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MFCR(3, 9)
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andi v1, 0x1
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bnez v1, 3b
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nop
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addi t2, 1
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bne t3, t2, 1b
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nop
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.set pop
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.endm
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VECTOR(XLPResetEntry, unknown)
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mfc0 t0, MIPS_COP_0_STATUS
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li t1, 0x80000
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and t1, t0, t1
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bnez t1, nmi_handler
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nop
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#ifdef SMP
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/* Reset entry for secordary cores */
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mfc0 t0, MIPS_COP_0_PRID, 1
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srl t0, t0, 2 /* discard thread id */
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andi t0, t0, 0x7 /* core id */
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li t1, 1
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sll t0, t1, t0
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nor t0, t0, zero /* mask with core id bit clear */
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/* clear CPU non-coherent bit */
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li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
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lw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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lw t1, 0(t2) /* read-back ensures operation complete */
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sync
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dla t2, mpentry
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jr t2
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nop
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#endif
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nop
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/* NOT REACHED */
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VECTOR_END(XLPResetEntry)
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/* Not yet */
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nmi_handler:
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nop
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nop
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j nmi_handler
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#ifdef SMP
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/*
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* Enable other threads in the core, called from thread 0
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* of the core
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*/
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LEAF(xlp_enable_threads)
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/*
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* Save and restore callee saved registers of all ABIs
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* Enabling threads trashes the registers
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*/
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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ori sp, sp, 0x7
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xori sp, sp, 0x7 /* align 64 bit */
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addiu sp, sp, -128
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mfc0 t1, MIPS_COP_0_STATUS
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sd s0, 0(sp)
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sd s1, 8(sp)
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sd s2, 16(sp)
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sd s3, 24(sp)
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sd s4, 32(sp)
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sd s5, 40(sp)
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sd s6, 48(sp)
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sd s7, 56(sp)
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sd s8, 64(sp)
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sd t1, 72(sp)
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sd gp, 80(sp)
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sd ra, 88(sp)
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flush_l1_dcache
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/* Use register number to work in o32 and n32 */
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li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
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move $8, a0
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sync
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MTCR(8, 9)
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mfc0 t0, MIPS_COP_0_PRID, 1
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andi t0, 0x3
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beqz t0, 2f
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nop
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dla t1, mpentry /* child thread, go to hardware init */
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jr t1
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nop
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2: /*
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* Parent hardware thread, restore registers, return
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*/
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#if 1
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/*
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* A0 Errata - Write MMU_SETUP after changing thread mode register.
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*/
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li $9, 0x400
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li $8, 0
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MTCR(8, 9)
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sll zero,3 /* ehb */
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#endif
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dmfc0 t0, $4, 2 /* SP saved in UserLocal */
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ori sp, t0, 0x7
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xori sp, sp, 0x7 /* align 64 bit */
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addiu sp, sp, -128
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ld s0, 0(sp)
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ld s1, 8(sp)
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ld s2, 16(sp)
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ld s3, 24(sp)
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ld s4, 32(sp)
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ld s5, 40(sp)
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ld s6, 48(sp)
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ld s7, 56(sp)
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ld s8, 64(sp)
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ld t1, 72(sp)
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ld gp, 80(sp)
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ld ra, 88(sp)
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mfc0 t1, MIPS_COP_0_STATUS
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move sp, t0 /* Restore the real SP */
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jr ra
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nop
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END(xlp_enable_threads)
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#endif
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