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b50d8083ab
ar724x_pci.c. * Move out the code which populates the firmware into ar71xx_fixup.c * Shuffle around the ar724x fixup code to match what the ar71xx fixup code does. I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't yet load, as the AR9285 EEPROM code needs to be made "flash aware." TODO: * Validate that I haven't broken AR71xx * Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes * Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from Linux OpenWRT. The current WAR has only been tested on the AR7240 and I'm not sure the way the BAR register is treated is "right". The "fixup" method here is right when setting the BAR for local access - ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242), but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the initial "fixup" BAR. It then restores the original BAR. I'll have to read the ar724x PCI bus glue to see what other special cases await.
27 lines
994 B
Plaintext
27 lines
994 B
Plaintext
# $FreeBSD$
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mips/atheros/apb.c standard
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mips/atheros/ar71xx_gpio.c optional gpio
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mips/atheros/ar71xx_machdep.c standard
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mips/atheros/ar71xx_ehci.c optional ehci
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mips/atheros/ar71xx_ohci.c optional ohci
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mips/atheros/ar71xx_pci.c optional ar71xx_pci pci
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mips/atheros/ar724x_pci.c optional ar724x_pci pci
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mips/atheros/ar71xx_pci_bus_space.c optional pci
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mips/atheros/ar71xx_spi.c optional ar71xx_spi
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mips/atheros/pcf2123_rtc.c optional pcf2123_rtc ar71xx_spi
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mips/atheros/ar71xx_wdog.c optional ar71xx_wdog
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mips/atheros/if_arge.c optional arge
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mips/atheros/uart_bus_ar71xx.c optional uart
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mips/atheros/uart_cpu_ar71xx.c optional uart
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mips/atheros/ar71xx_bus_space_reversed.c standard
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mips/mips/intr_machdep.c standard
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mips/mips/tick.c standard
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mips/atheros/ar71xx_setup.c standard
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mips/atheros/ar71xx_chip.c standard
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mips/atheros/ar724x_chip.c standard
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mips/atheros/ar91xx_chip.c standard
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mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom
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dev/hwpmc/hwpmc_mips24k.c optional hwpmc
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