mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-29 12:03:03 +00:00
3120 lines
87 KiB
C
3120 lines
87 KiB
C
/*
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* $FreeBSD$
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*/
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/* This file is automatically generated --- do not edit */
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struct reg_info t3c_sge3_regs[] = {
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{ "SG_CONTROL", 0x0, 0 },
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{ "CongMode", 29, 1 },
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{ "TnlFLMode", 28, 1 },
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{ "FatlPerrEn", 27, 1 },
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{ "UrgTnl", 26, 1 },
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{ "NewNotify", 25, 1 },
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{ "AvoidCqOvfl", 24, 1 },
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{ "OptOneIntMultQ", 23, 1 },
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{ "CQCrdtCtrl", 22, 1 },
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{ "EgrEnUpBp", 21, 1 },
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{ "DropPkt", 20, 1 },
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{ "EgrGenCtrl", 19, 1 },
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{ "UserSpaceSize", 14, 5 },
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{ "HostPageSize", 11, 3 },
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{ "PCIRelax", 10, 1 },
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{ "FLMode", 9, 1 },
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{ "PktShift", 6, 3 },
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{ "OneIntMultQ", 5, 1 },
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{ "FLPickAvail", 4, 1 },
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{ "BigEndianEgress", 3, 1 },
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{ "BigEndianIngress", 2, 1 },
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{ "IscsiCoalescing", 1, 1 },
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{ "GlobalEnable", 0, 1 },
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{ "SG_KDOORBELL", 0x4, 0 },
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{ "SelEgrCntx", 31, 1 },
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{ "EgrCntx", 0, 16 },
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{ "SG_GTS", 0x8, 0 },
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{ "RspQ", 29, 3 },
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{ "NewTimer", 16, 13 },
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{ "NewIndex", 0, 16 },
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{ "SG_CONTEXT_CMD", 0xc, 0 },
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{ "Opcode", 28, 4 },
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{ "Busy", 27, 1 },
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{ "CQ_credit", 20, 7 },
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{ "CQ", 19, 1 },
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{ "RspQ", 18, 1 },
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{ "Egress", 17, 1 },
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{ "FreeList", 16, 1 },
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{ "Context", 0, 16 },
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{ "SG_CONTEXT_DATA0", 0x10, 0 },
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{ "SG_CONTEXT_DATA1", 0x14, 0 },
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{ "SG_CONTEXT_DATA2", 0x18, 0 },
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{ "SG_CONTEXT_DATA3", 0x1c, 0 },
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{ "SG_CONTEXT_MASK0", 0x20, 0 },
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{ "SG_CONTEXT_MASK1", 0x24, 0 },
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{ "SG_CONTEXT_MASK2", 0x28, 0 },
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{ "SG_CONTEXT_MASK3", 0x2c, 0 },
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{ "SG_RSPQ_CREDIT_RETURN", 0x30, 0 },
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{ "RspQ", 29, 3 },
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{ "Data", 0, 16 },
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{ "SG_DATA_INTR", 0x34, 0 },
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{ "ErrIntr", 31, 1 },
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{ "DataIntr", 0, 8 },
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{ "SG_HI_DRB_HI_THRSH", 0x38, 0 },
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{ "HiDrbHiThrsh", 0, 10 },
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{ "SG_HI_DRB_LO_THRSH", 0x3c, 0 },
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{ "HiDrbLoThrsh", 0, 10 },
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{ "SG_LO_DRB_HI_THRSH", 0x40, 0 },
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{ "LoDrbHiThrsh", 0, 10 },
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{ "SG_LO_DRB_LO_THRSH", 0x44, 0 },
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{ "LoDrbLoThrsh", 0, 10 },
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{ "SG_ONE_INT_MULT_Q_COALESCING_TIMER", 0x48, 0 },
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{ "SG_RSPQ_FL_STATUS", 0x4c, 0 },
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{ "RspQ0Starved", 0, 1 },
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{ "RspQ1Starved", 1, 1 },
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{ "RspQ2Starved", 2, 1 },
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{ "RspQ3Starved", 3, 1 },
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{ "RspQ4Starved", 4, 1 },
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{ "RspQ5Starved", 5, 1 },
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{ "RspQ6Starved", 6, 1 },
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{ "RspQ7Starved", 7, 1 },
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{ "RspQ0Disabled", 8, 1 },
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{ "RspQ1Disabled", 9, 1 },
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{ "RspQ2Disabled", 10, 1 },
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{ "RspQ3Disabled", 11, 1 },
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{ "RspQ4Disabled", 12, 1 },
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{ "RspQ5Disabled", 13, 1 },
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{ "RspQ6Disabled", 14, 1 },
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{ "RspQ7Disabled", 15, 1 },
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{ "FL0Empty", 16, 1 },
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{ "FL1Empty", 17, 1 },
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{ "FL2Empty", 18, 1 },
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{ "FL3Empty", 19, 1 },
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{ "FL4Empty", 20, 1 },
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{ "FL5Empty", 21, 1 },
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{ "FL6Empty", 22, 1 },
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{ "FL7Empty", 23, 1 },
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{ "FL8Empty", 24, 1 },
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{ "FL9Empty", 25, 1 },
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{ "FL10Empty", 26, 1 },
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{ "FL11Empty", 27, 1 },
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{ "FL12Empty", 28, 1 },
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{ "FL13Empty", 29, 1 },
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{ "FL14Empty", 30, 1 },
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{ "FL15Empty", 31, 1 },
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{ "SG_EGR_PRI_CNT", 0x50, 0 },
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{ "EgrErrOpCode", 24, 8 },
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{ "EgrHiOpCode", 16, 8 },
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{ "EgrLoOpCode", 8, 8 },
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{ "EgrPriCnt", 0, 5 },
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{ "SG_EGR_RCQ_DRB_THRSH", 0x54, 0 },
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{ "HiRcqDrbThrsh", 16, 11 },
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{ "LoRcqDrbThrsh", 0, 11 },
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{ "SG_EGR_CNTX_BADDR", 0x58, 0 },
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{ "EgrCntxBAddr", 5, 27 },
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{ "SG_INT_CAUSE", 0x5c, 0 },
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{ "HiRcqParityError", 31, 1 },
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{ "LoRcqParityError", 30, 1 },
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{ "HiDrbParityError", 29, 1 },
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{ "LoDrbParityError", 28, 1 },
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{ "FlParityError", 22, 6 },
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{ "ItParityError", 20, 2 },
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{ "IrParityError", 19, 1 },
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{ "RcParityError", 18, 1 },
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{ "OcParityError", 17, 1 },
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{ "CpParityError", 16, 1 },
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{ "R_Req_FramingError", 15, 1 },
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{ "UC_Req_FramingError", 14, 1 },
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{ "HiCtlDrbDropErr", 13, 1 },
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{ "LoCtlDrbDropErr", 12, 1 },
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{ "HiPioDrbDropErr", 11, 1 },
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{ "LoPioDrbDropErr", 10, 1 },
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{ "HiCrdtUndFlowErr", 9, 1 },
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{ "LoCrdtUndFlowErr", 8, 1 },
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{ "HiPriorityDBFull", 7, 1 },
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{ "HiPriorityDBEmpty", 6, 1 },
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{ "LoPriorityDBFull", 5, 1 },
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{ "LoPriorityDBEmpty", 4, 1 },
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{ "RspQDisabled", 3, 1 },
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{ "RspQCreditOverfow", 2, 1 },
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{ "FlEmpty", 1, 1 },
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{ "RspQStarve", 0, 1 },
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{ "SG_INT_ENABLE", 0x60, 0 },
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{ "HiRcqParityError", 31, 1 },
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{ "LoRcqParityError", 30, 1 },
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{ "HiDrbParityError", 29, 1 },
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{ "LoDrbParityError", 28, 1 },
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{ "FlParityError", 22, 6 },
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{ "ItParityError", 20, 2 },
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{ "IrParityError", 19, 1 },
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{ "RcParityError", 18, 1 },
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{ "OcParityError", 17, 1 },
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{ "CpParityError", 16, 1 },
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{ "R_Req_FramingError", 15, 1 },
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{ "UC_Req_FramingError", 14, 1 },
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{ "HiCtlDrbDropErr", 13, 1 },
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{ "LoCtlDrbDropErr", 12, 1 },
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{ "HiPioDrbDropErr", 11, 1 },
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{ "LoPioDrbDropErr", 10, 1 },
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{ "HiCrdtUndFlowErr", 9, 1 },
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{ "LoCrdtUndFlowErr", 8, 1 },
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{ "HiPriorityDBFull", 7, 1 },
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{ "HiPriorityDBEmpty", 6, 1 },
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{ "LoPriorityDBFull", 5, 1 },
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{ "LoPriorityDBEmpty", 4, 1 },
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{ "RspQDisabled", 3, 1 },
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{ "RspQCreditOverfow", 2, 1 },
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{ "FlEmpty", 1, 1 },
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{ "RspQStarve", 0, 1 },
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{ "SG_CMDQ_CREDIT_TH", 0x64, 0 },
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{ "Timeout", 8, 24 },
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{ "Threshold", 0, 8 },
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{ "SG_TIMER_TICK", 0x68, 0 },
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{ "SG_CQ_CONTEXT_BADDR", 0x6c, 0 },
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{ "baseAddr", 5, 27 },
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{ "SG_OCO_BASE", 0x70, 0 },
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{ "Base1", 16, 16 },
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{ "Base0", 0, 16 },
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{ "SG_DRB_PRI_THRESH", 0x74, 0 },
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{ "DrbPriThrsh", 0, 16 },
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{ "SG_DEBUG_INDEX", 0x78, 0 },
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{ "SG_DEBUG_DATA", 0x7c, 0 },
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{ NULL, 0, 0 }
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};
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struct reg_info t3c_pcix1_regs[] = {
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{ "PCIX_INT_ENABLE", 0x80, 0 },
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{ "MSIXParErr", 22, 3 },
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{ "CFParErr", 18, 4 },
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{ "RFParErr", 14, 4 },
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{ "WFParErr", 12, 2 },
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{ "PIOParErr", 11, 1 },
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{ "DetUncECCErr", 10, 1 },
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{ "DetCorECCErr", 9, 1 },
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{ "RcvSplCmpErr", 8, 1 },
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{ "UnxSplCmp", 7, 1 },
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{ "SplCmpDis", 6, 1 },
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{ "DetParErr", 5, 1 },
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{ "SigSysErr", 4, 1 },
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{ "RcvMstAbt", 3, 1 },
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{ "RcvTarAbt", 2, 1 },
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{ "SigTarAbt", 1, 1 },
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{ "MstDetParErr", 0, 1 },
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{ "PCIX_INT_CAUSE", 0x84, 0 },
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{ "MSIXParErr", 22, 3 },
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{ "CFParErr", 18, 4 },
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{ "RFParErr", 14, 4 },
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{ "WFParErr", 12, 2 },
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{ "PIOParErr", 11, 1 },
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{ "DetUncECCErr", 10, 1 },
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{ "DetCorECCErr", 9, 1 },
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{ "RcvSplCmpErr", 8, 1 },
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{ "UnxSplCmp", 7, 1 },
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{ "SplCmpDis", 6, 1 },
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{ "DetParErr", 5, 1 },
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{ "SigSysErr", 4, 1 },
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{ "RcvMstAbt", 3, 1 },
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{ "RcvTarAbt", 2, 1 },
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{ "SigTarAbt", 1, 1 },
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{ "MstDetParErr", 0, 1 },
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{ "PCIX_CFG", 0x88, 0 },
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{ "DMAStopEn", 19, 1 },
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{ "CLIDecEn", 18, 1 },
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{ "LatTmrDis", 17, 1 },
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{ "LowPwrEn", 16, 1 },
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{ "AsyncIntVec", 11, 5 },
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{ "MaxSplTrnC", 8, 3 },
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{ "MaxSplTrnR", 5, 3 },
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{ "MaxWrByteCnt", 3, 2 },
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{ "WrReqAtomicEn", 2, 1 },
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{ "CRstWrmMode", 1, 1 },
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{ "PIOAck64En", 0, 1 },
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{ "PCIX_MODE", 0x8c, 0 },
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{ "PClkRange", 6, 2 },
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{ "PCIXInitPat", 2, 4 },
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{ "66MHz", 1, 1 },
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{ "64Bit", 0, 1 },
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{ "PCIX_CAL", 0x90, 0 },
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{ "Busy", 31, 1 },
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{ "PerCalDiv", 22, 8 },
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{ "PerCalEn", 21, 1 },
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{ "SglCalEn", 20, 1 },
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{ "ZInUpdMode", 19, 1 },
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{ "ZInSel", 18, 1 },
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{ "ZPDMan", 15, 3 },
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{ "ZPUMan", 12, 3 },
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{ "ZPDOut", 9, 3 },
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{ "ZPUOut", 6, 3 },
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{ "ZPDIn", 3, 3 },
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{ "ZPUIn", 0, 3 },
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{ "PCIX_WOL", 0x94, 0 },
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{ "WakeUp1", 3, 1 },
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{ "WakeUp0", 2, 1 },
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{ "SleepMode1", 1, 1 },
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{ "SleepMode0", 0, 1 },
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{ "PCIX_STAT0", 0x98, 0 },
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{ "PIOReqFifoLevel", 26, 6 },
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{ "RFIniSt", 24, 2 },
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{ "RFRespRdSt", 22, 2 },
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{ "TarCSt", 19, 3 },
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{ "TarXSt", 16, 3 },
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{ "WFReqWrSt", 13, 3 },
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{ "WFRespFifoEmpty", 12, 1 },
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{ "WFReqFifoEmpty", 11, 1 },
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{ "RFRespFifoEmpty", 10, 1 },
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{ "RFReqFifoEmpty", 9, 1 },
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{ "PIORespFifoLevel", 7, 2 },
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{ "CFRespFifoEmpty", 6, 1 },
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{ "CFReqFifoEmpty", 5, 1 },
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{ "VPDRespFifoEmpty", 4, 1 },
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{ "VPDReqFifoEmpty", 3, 1 },
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{ "PIO_RspPnd", 2, 1 },
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{ "DlyTrnPnd", 1, 1 },
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{ "SplTrnPnd", 0, 1 },
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{ "PCIX_STAT1", 0x9c, 0 },
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{ "WFIniSt", 26, 4 },
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{ "ArbSt", 23, 3 },
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{ "PMISt", 21, 2 },
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{ "CalSt", 19, 2 },
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{ "CFReqRdSt", 17, 2 },
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{ "CFIniSt", 15, 2 },
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{ "CFRespRdSt", 13, 2 },
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{ "IniCSt", 10, 3 },
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{ "IniXSt", 7, 3 },
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{ "IntSt", 4, 3 },
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{ "PIOSt", 2, 2 },
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{ "RFReqRdSt", 0, 2 },
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{ NULL, 0, 0 }
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};
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struct reg_info t3c_pcie0_regs[] = {
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{ "PCIE_INT_ENABLE", 0x80, 0 },
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{ "BISTErr", 19, 8 },
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{ "TxParErr", 18, 1 },
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{ "RxParErr", 17, 1 },
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{ "RetryLUTParErr", 16, 1 },
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{ "RetryBUFParErr", 15, 1 },
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{ "MSIXParErr", 12, 3 },
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{ "CFParErr", 11, 1 },
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{ "RFParErr", 10, 1 },
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{ "WFParErr", 9, 1 },
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{ "PIOParErr", 8, 1 },
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{ "UnxSplCplErrC", 7, 1 },
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{ "UnxSplCplErrR", 6, 1 },
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{ "VPDAddrChng", 5, 1 },
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{ "BusMstrEn", 4, 1 },
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{ "PMStChng", 3, 1 },
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{ "PEXMsg", 2, 1 },
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{ "ZeroLenRd", 1, 1 },
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{ "PEXErr", 0, 1 },
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{ "PCIE_INT_CAUSE", 0x84, 0 },
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{ "BISTErr", 19, 8 },
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{ "TxParErr", 18, 1 },
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{ "RxParErr", 17, 1 },
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{ "RetryLUTParErr", 16, 1 },
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{ "RetryBUFParErr", 15, 1 },
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{ "MSIXParErr", 12, 3 },
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{ "CFParErr", 11, 1 },
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{ "RFParErr", 10, 1 },
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{ "WFParErr", 9, 1 },
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{ "PIOParErr", 8, 1 },
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{ "UnxSplCplErrC", 7, 1 },
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{ "UnxSplCplErrR", 6, 1 },
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{ "VPDAddrChng", 5, 1 },
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{ "BusMstrEn", 4, 1 },
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{ "PMStChng", 3, 1 },
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{ "PEXMsg", 2, 1 },
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{ "ZeroLenRd", 1, 1 },
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{ "PEXErr", 0, 1 },
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{ "PCIE_CFG", 0x88, 0 },
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{ "DMAStopEn", 24, 1 },
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{ "PriorityINTA", 23, 1 },
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{ "IniFullPkt", 22, 1 },
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{ "EnableLinkDwnDRst", 21, 1 },
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{ "EnableLinkDownRst", 20, 1 },
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{ "EnableHotRst", 19, 1 },
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{ "IniWaitForGnt", 18, 1 },
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{ "IniBEDis", 17, 1 },
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{ "CLIDecEn", 16, 1 },
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{ "AsyncIntVec", 11, 5 },
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{ "MaxSplTrnC", 7, 4 },
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{ "MaxSplTrnR", 1, 6 },
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{ "CRstWrmMode", 0, 1 },
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{ "PCIE_MODE", 0x8c, 0 },
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{ "TAR_State", 29, 3 },
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{ "RF_StateIni", 26, 3 },
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{ "CF_StateIni", 23, 3 },
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{ "PIO_StatePL", 20, 3 },
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{ "PIO_StateISC", 18, 2 },
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{ "NumFstTrnSeqRx", 10, 8 },
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{ "LnkCntlState", 2, 8 },
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{ "VC0Up", 1, 1 },
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{ "LnkInitial", 0, 1 },
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{ "PCIE_STAT", 0x90, 0 },
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{ "INI_State", 28, 4 },
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{ "WF_StateIni", 24, 4 },
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{ "PLM_ReqFIFOCnt", 22, 2 },
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{ "ER_ReqFIFOEmpty", 21, 1 },
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{ "WF_RspFIFOEmpty", 20, 1 },
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{ "WF_ReqFIFOEmpty", 19, 1 },
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{ "RF_RspFIFOEmpty", 18, 1 },
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{ "RF_ReqFIFOEmpty", 17, 1 },
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{ "RF_ActEmpty", 16, 1 },
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{ "PIO_RspFIFOCnt", 11, 5 },
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{ "PIO_ReqFIFOCnt", 5, 6 },
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{ "CF_RspFIFOEmpty", 4, 1 },
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{ "CF_ReqFIFOEmpty", 3, 1 },
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{ "CF_ActEmpty", 2, 1 },
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{ "VPD_RspFIFOEmpty", 1, 1 },
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{ "VPD_ReqFIFOEmpty", 0, 1 },
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{ "PCIE_WOL", 0x94, 0 },
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{ "CF_RspState", 12, 2 },
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{ "RF_RspState", 10, 2 },
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{ "PME_State", 7, 3 },
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{ "INT_State", 4, 3 },
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{ "WakeUp1", 3, 1 },
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{ "WakeUp0", 2, 1 },
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{ "SleepMode1", 1, 1 },
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{ "SleepMode0", 0, 1 },
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{ "PCIE_PEX_CTRL0", 0x98, 0 },
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{ "CplTimeoutRetry", 31, 1 },
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{ "StrictTSMN", 30, 1 },
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{ "NumFstTrnSeq", 22, 8 },
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{ "ReplayLmt", 2, 20 },
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{ "TxPndChkEn", 1, 1 },
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{ "CplPndChkEn", 0, 1 },
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{ "PCIE_PEX_CTRL1", 0x9c, 0 },
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{ "RxPhyErrEn", 31, 1 },
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{ "DLLPTimeoutLmt", 13, 18 },
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{ "AckLat", 0, 13 },
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{ "PCIE_PEX_CTRL2", 0xa0, 0 },
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{ "LnkCntlDetDir", 30, 1 },
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{ "EnterL1rEn", 29, 1 },
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{ "PMExitL1Req", 28, 1 },
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{ "PMTxIdle", 27, 1 },
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{ "PCIModeLoop", 26, 1 },
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{ "L1ASPMTxRxL0sTime", 14, 12 },
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|
{ "L0sIdleTime", 3, 11 },
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|
{ "EnterL1ASPMEn", 2, 1 },
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{ "EnterL1En", 1, 1 },
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{ "EnterL0sEn", 0, 1 },
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{ "PCIE_PEX_ERR", 0xa4, 0 },
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|
{ "CplTimeoutID", 18, 7 },
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{ "FlowCtlOFlowErr", 17, 1 },
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|
{ "ReplayTimeout", 16, 1 },
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|
{ "ReplayRollover", 15, 1 },
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{ "BadDLLP", 14, 1 },
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|
{ "DLLPErr", 13, 1 },
|
|
{ "FlowCtlProtErr", 12, 1 },
|
|
{ "CplTimeout", 11, 1 },
|
|
{ "PHYRcvErr", 10, 1 },
|
|
{ "DisTLP", 9, 1 },
|
|
{ "BadECRC", 8, 1 },
|
|
{ "BadTLP", 7, 1 },
|
|
{ "MalTLP", 6, 1 },
|
|
{ "UnxCpl", 5, 1 },
|
|
{ "UnsReq", 4, 1 },
|
|
{ "PsnReq", 3, 1 },
|
|
{ "UnsCpl", 2, 1 },
|
|
{ "CplAbt", 1, 1 },
|
|
{ "PsnCpl", 0, 1 },
|
|
{ "PCIE_SERDES_CTRL", 0xa8, 0 },
|
|
{ "PMASel", 3, 1 },
|
|
{ "Lane", 0, 3 },
|
|
{ "PCIE_SERDES_QUAD_CTRL0", 0xac, 0 },
|
|
{ "TestSig", 10, 19 },
|
|
{ "Offset", 2, 8 },
|
|
{ "OffsetEn", 1, 1 },
|
|
{ "IDDQb", 0, 1 },
|
|
{ "PCIE_SERDES_QUAD_CTRL1", 0xb0, 0 },
|
|
{ "FastInit", 28, 1 },
|
|
{ "CTCDisable", 27, 1 },
|
|
{ "ManResetPLL", 26, 1 },
|
|
{ "ManL2Pwrdn", 25, 1 },
|
|
{ "ManQuadEn", 24, 1 },
|
|
{ "RxEqCtl", 22, 2 },
|
|
{ "HiVMode", 21, 1 },
|
|
{ "RefSel", 19, 2 },
|
|
{ "RxTermAdj", 17, 2 },
|
|
{ "TxTermAdj", 15, 2 },
|
|
{ "Deq", 11, 4 },
|
|
{ "Dtx", 7, 4 },
|
|
{ "LoDrv", 6, 1 },
|
|
{ "HiDrv", 5, 1 },
|
|
{ "IntParReset", 4, 1 },
|
|
{ "IntParLPBK", 3, 1 },
|
|
{ "IntSerLPBKwDrv", 2, 1 },
|
|
{ "PW", 1, 1 },
|
|
{ "PClkDetect", 0, 1 },
|
|
{ "PCIE_SERDES_LANE_CTRL", 0xb4, 0 },
|
|
{ "ExtBISTChkErrClr", 22, 1 },
|
|
{ "ExtBISTChkEn", 21, 1 },
|
|
{ "ExtBISTGenEn", 20, 1 },
|
|
{ "ExtBISTPat", 17, 3 },
|
|
{ "ExtParReset", 16, 1 },
|
|
{ "ExtParLPBK", 15, 1 },
|
|
{ "ManRxTermEn", 14, 1 },
|
|
{ "ManBeaconTxEn", 13, 1 },
|
|
{ "ManRxDetectEn", 12, 1 },
|
|
{ "ManTxIdleEn", 11, 1 },
|
|
{ "ManRxIdleEn", 10, 1 },
|
|
{ "ManL1Pwrdn", 9, 1 },
|
|
{ "ManReset", 8, 1 },
|
|
{ "ManFmOffset", 3, 5 },
|
|
{ "ManFmOffsetEn", 2, 1 },
|
|
{ "ManLaneEn", 1, 1 },
|
|
{ "IntSerLPBK", 0, 1 },
|
|
{ "PCIE_SERDES_LANE_STAT", 0xb8, 0 },
|
|
{ "ExtBISTChkErrCnt", 8, 24 },
|
|
{ "ExtBISTChkFmd", 7, 1 },
|
|
{ "BeaconDetectChg", 6, 1 },
|
|
{ "RxDetectChg", 5, 1 },
|
|
{ "TxIdleDetectChg", 4, 1 },
|
|
{ "BeaconDetect", 2, 1 },
|
|
{ "RxDetect", 1, 1 },
|
|
{ "TxIdleDetect", 0, 1 },
|
|
{ "PCIE_PEX_WMARK", 0xbc, 0 },
|
|
{ "P_WMark", 18, 11 },
|
|
{ "NP_WMark", 11, 7 },
|
|
{ "CPL_WMark", 0, 11 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_t3dbg_regs[] = {
|
|
{ "T3DBG_DBG0_CFG", 0xc0, 0 },
|
|
{ "RegSelect", 9, 8 },
|
|
{ "ModuleSelect", 4, 5 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "T3DBG_DBG0_EN", 0xc4, 0 },
|
|
{ "SDRByte0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "T3DBG_DBG1_CFG", 0xc8, 0 },
|
|
{ "RegSelect", 9, 8 },
|
|
{ "ModuleSelect", 4, 5 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "T3DBG_DBG1_EN", 0xcc, 0 },
|
|
{ "SDRByte0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "T3DBG_GPIO_EN", 0xd0, 0 },
|
|
{ "GPIO11_OEn", 27, 1 },
|
|
{ "GPIO10_OEn", 26, 1 },
|
|
{ "GPIO9_OEn", 25, 1 },
|
|
{ "GPIO8_OEn", 24, 1 },
|
|
{ "GPIO7_OEn", 23, 1 },
|
|
{ "GPIO6_OEn", 22, 1 },
|
|
{ "GPIO5_OEn", 21, 1 },
|
|
{ "GPIO4_OEn", 20, 1 },
|
|
{ "GPIO3_OEn", 19, 1 },
|
|
{ "GPIO2_OEn", 18, 1 },
|
|
{ "GPIO1_OEn", 17, 1 },
|
|
{ "GPIO0_OEn", 16, 1 },
|
|
{ "GPIO11_Out_Val", 11, 1 },
|
|
{ "GPIO10_Out_Val", 10, 1 },
|
|
{ "GPIO9_Out_Val", 9, 1 },
|
|
{ "GPIO8_Out_Val", 8, 1 },
|
|
{ "GPIO7_Out_Val", 7, 1 },
|
|
{ "GPIO6_Out_Val", 6, 1 },
|
|
{ "GPIO5_Out_Val", 5, 1 },
|
|
{ "GPIO4_Out_Val", 4, 1 },
|
|
{ "GPIO3_Out_Val", 3, 1 },
|
|
{ "GPIO2_Out_Val", 2, 1 },
|
|
{ "GPIO1_Out_Val", 1, 1 },
|
|
{ "GPIO0_Out_Val", 0, 1 },
|
|
{ "T3DBG_GPIO_IN", 0xd4, 0 },
|
|
{ "GPIO11_CHG_DET", 27, 1 },
|
|
{ "GPIO10_CHG_DET", 26, 1 },
|
|
{ "GPIO9_CHG_DET", 25, 1 },
|
|
{ "GPIO8_CHG_DET", 24, 1 },
|
|
{ "GPIO7_CHG_DET", 23, 1 },
|
|
{ "GPIO6_CHG_DET", 22, 1 },
|
|
{ "GPIO5_CHG_DET", 21, 1 },
|
|
{ "GPIO4_CHG_DET", 20, 1 },
|
|
{ "GPIO3_CHG_DET", 19, 1 },
|
|
{ "GPIO2_CHG_DET", 18, 1 },
|
|
{ "GPIO1_CHG_DET", 17, 1 },
|
|
{ "GPIO0_CHG_DET", 16, 1 },
|
|
{ "GPIO11_IN", 11, 1 },
|
|
{ "GPIO10_IN", 10, 1 },
|
|
{ "GPIO9_IN", 9, 1 },
|
|
{ "GPIO8_IN", 8, 1 },
|
|
{ "GPIO7_IN", 7, 1 },
|
|
{ "GPIO6_IN", 6, 1 },
|
|
{ "GPIO5_IN", 5, 1 },
|
|
{ "GPIO4_IN", 4, 1 },
|
|
{ "GPIO3_IN", 3, 1 },
|
|
{ "GPIO2_IN", 2, 1 },
|
|
{ "GPIO1_IN", 1, 1 },
|
|
{ "GPIO0_IN", 0, 1 },
|
|
{ "T3DBG_INT_ENABLE", 0xd8, 0 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "R_LOCK", 18, 1 },
|
|
{ "PX_LOCK", 17, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "T3DBG_INT_CAUSE", 0xdc, 0 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "R_LOCK", 18, 1 },
|
|
{ "PX_LOCK", 17, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "T3DBG_DBG0_RST_VALUE", 0xe0, 0 },
|
|
{ "DebugData", 0, 8 },
|
|
{ "T3DBG_PLL_OCLK_PAD_EN", 0xe4, 0 },
|
|
{ "PCIE_OCLK_En", 20, 1 },
|
|
{ "PClkTree_DBG_En", 17, 1 },
|
|
{ "PCIX_OCLK_En", 16, 1 },
|
|
{ "U_OCLK_En", 12, 1 },
|
|
{ "R_OCLK_En", 8, 1 },
|
|
{ "M_OCLK_En", 4, 1 },
|
|
{ "C_OCLK_En", 0, 1 },
|
|
{ "T3DBG_PLL_LOCK", 0xe8, 0 },
|
|
{ "PCIX_LOCK", 16, 1 },
|
|
{ "U_LOCK", 12, 1 },
|
|
{ "R_LOCK", 8, 1 },
|
|
{ "M_LOCK", 4, 1 },
|
|
{ "C_LOCK", 0, 1 },
|
|
{ "T3DBG_SERDES_RBC_CFG", 0xec, 0 },
|
|
{ "X_RBC_Lane_Sel", 16, 2 },
|
|
{ "X_RBC_Dbg_En", 12, 1 },
|
|
{ "X_Serdes_Sel", 8, 1 },
|
|
{ "PE_RBC_Lane_Sel", 4, 3 },
|
|
{ "PE_RBC_Dbg_En", 0, 1 },
|
|
{ "T3DBG_GPIO_ACT_LOW", 0xf0, 0 },
|
|
{ "C_LOCK_ACT_LOW", 21, 1 },
|
|
{ "M_LOCK_ACT_LOW", 20, 1 },
|
|
{ "U_LOCK_ACT_LOW", 19, 1 },
|
|
{ "R_LOCK_ACT_LOW", 18, 1 },
|
|
{ "PX_LOCK_ACT_LOW", 17, 1 },
|
|
{ "GPIO11_ACT_LOW", 11, 1 },
|
|
{ "GPIO10_ACT_LOW", 10, 1 },
|
|
{ "GPIO9_ACT_LOW", 9, 1 },
|
|
{ "GPIO8_ACT_LOW", 8, 1 },
|
|
{ "GPIO7_ACT_LOW", 7, 1 },
|
|
{ "GPIO6_ACT_LOW", 6, 1 },
|
|
{ "GPIO5_ACT_LOW", 5, 1 },
|
|
{ "GPIO4_ACT_LOW", 4, 1 },
|
|
{ "GPIO3_ACT_LOW", 3, 1 },
|
|
{ "GPIO2_ACT_LOW", 2, 1 },
|
|
{ "GPIO1_ACT_LOW", 1, 1 },
|
|
{ "GPIO0_ACT_LOW", 0, 1 },
|
|
{ "T3DBG_PMON_CFG", 0xf4, 0 },
|
|
{ "PMON_DONE", 29, 1 },
|
|
{ "PMON_FAIL", 28, 1 },
|
|
{ "PMON_FDEL_AUTO", 22, 6 },
|
|
{ "PMON_CDEL_AUTO", 16, 6 },
|
|
{ "PMON_FDEL_MANUAL", 10, 6 },
|
|
{ "PMON_CDEL_MANUAL", 4, 6 },
|
|
{ "PMON_MANUAL", 1, 1 },
|
|
{ "PMON_AUTO", 0, 1 },
|
|
{ "T3DBG_SERDES_REFCLK_CFG", 0xf8, 0 },
|
|
{ "PE_REFCLK_DBG_EN", 12, 1 },
|
|
{ "X_REFCLK_DBG_EN", 8, 1 },
|
|
{ "PE_REFCLK_TERMADJ", 5, 2 },
|
|
{ "PE_REFCLK_PD", 4, 1 },
|
|
{ "X_REFCLK_TERMADJ", 1, 2 },
|
|
{ "X_REFCLK_PD", 0, 1 },
|
|
{ "T3DBG_PCIE_PMA_BSPIN_CFG", 0xfc, 0 },
|
|
{ "BSModeQuad1", 31, 1 },
|
|
{ "BSInSelLane7", 29, 2 },
|
|
{ "BSEnLane7", 28, 1 },
|
|
{ "BSInSelLane6", 25, 2 },
|
|
{ "BSEnLane6", 24, 1 },
|
|
{ "BSInSelLane5", 21, 2 },
|
|
{ "BSEnLane5", 20, 1 },
|
|
{ "BSInSelLane4", 17, 2 },
|
|
{ "BSEnLane4", 16, 1 },
|
|
{ "BSModeQuad0", 15, 1 },
|
|
{ "BSInSelLane3", 13, 2 },
|
|
{ "BSEnLane3", 12, 1 },
|
|
{ "BSInSelLane2", 9, 2 },
|
|
{ "BSEnLane2", 8, 1 },
|
|
{ "BSInSelLane1", 5, 2 },
|
|
{ "BSEnLane1", 4, 1 },
|
|
{ "BSInSelLane0", 1, 2 },
|
|
{ "BSEnLane0", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mc7_pmrx_regs[] = {
|
|
{ "MC7_CFG", 0x100, 0 },
|
|
{ "ImpSetUpdate", 14, 1 },
|
|
{ "IFEn", 13, 1 },
|
|
{ "TERM300", 12, 1 },
|
|
{ "TERM150", 11, 1 },
|
|
{ "Slow", 10, 1 },
|
|
{ "Width", 8, 2 },
|
|
{ "ODTEn", 7, 1 },
|
|
{ "Bks", 6, 1 },
|
|
{ "Org", 5, 1 },
|
|
{ "Den", 2, 3 },
|
|
{ "Rdy", 1, 1 },
|
|
{ "ClkEn", 0, 1 },
|
|
{ "MC7_MODE", 0x104, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Mode", 0, 16 },
|
|
{ "MC7_EXT_MODE1", 0x108, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "OCDAdjustMode", 20, 1 },
|
|
{ "OCDCode", 16, 4 },
|
|
{ "ExtMode1", 0, 16 },
|
|
{ "MC7_EXT_MODE2", 0x10c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode2", 0, 16 },
|
|
{ "MC7_EXT_MODE3", 0x110, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode3", 0, 16 },
|
|
{ "MC7_PRE", 0x114, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "MC7_REF", 0x118, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "PreRefDiv", 1, 14 },
|
|
{ "PerRefEn", 0, 1 },
|
|
{ "MC7_DLL", 0x11c, 0 },
|
|
{ "DLLLock", 31, 1 },
|
|
{ "DLLDelta", 24, 7 },
|
|
{ "ManDelta", 3, 7 },
|
|
{ "DLLDeltaSel", 2, 1 },
|
|
{ "DLLEnb", 1, 1 },
|
|
{ "DLLRst", 0, 1 },
|
|
{ "MC7_PARM", 0x120, 0 },
|
|
{ "ActToPreDly", 26, 4 },
|
|
{ "ActToRdWrDly", 23, 3 },
|
|
{ "PreCyc", 20, 3 },
|
|
{ "RefCyc", 13, 7 },
|
|
{ "BkCyc", 8, 5 },
|
|
{ "WrToRdDly", 4, 4 },
|
|
{ "RdToWrDly", 0, 4 },
|
|
{ "MC7_HWM_WRR", 0x124, 0 },
|
|
{ "MEM_HWM", 26, 6 },
|
|
{ "ULP_HWM", 22, 4 },
|
|
{ "TOT_RLD_WT", 14, 8 },
|
|
{ "MEM_RLD_WT", 7, 7 },
|
|
{ "ULP_RLD_WT", 0, 7 },
|
|
{ "MC7_CAL", 0x128, 0 },
|
|
{ "BUSY", 31, 1 },
|
|
{ "CAL_FAULT", 30, 1 },
|
|
{ "PER_CAL_DIV", 22, 8 },
|
|
{ "PER_CAL_EN", 21, 1 },
|
|
{ "SGL_CAL_EN", 20, 1 },
|
|
{ "IMP_UPD_MODE", 19, 1 },
|
|
{ "IMP_SEL", 18, 1 },
|
|
{ "IMP_MAN_PD", 15, 3 },
|
|
{ "IMP_MAN_PU", 12, 3 },
|
|
{ "IMP_CAL_PD", 9, 3 },
|
|
{ "IMP_CAL_PU", 6, 3 },
|
|
{ "IMP_SET_PD", 3, 3 },
|
|
{ "IMP_SET_PU", 0, 3 },
|
|
{ "MC7_ERR_ADDR", 0x12c, 0 },
|
|
{ "ErrAddress", 3, 29 },
|
|
{ "ErrAgent", 1, 2 },
|
|
{ "ErrOp", 0, 1 },
|
|
{ "MC7_ECC", 0x130, 0 },
|
|
{ "UECnt", 10, 8 },
|
|
{ "CECnt", 2, 8 },
|
|
{ "ECCChkEn", 1, 1 },
|
|
{ "ECCGenEn", 0, 1 },
|
|
{ "MC7_CE_ADDR", 0x134, 0 },
|
|
{ "MC7_CE_DATA0", 0x138, 0 },
|
|
{ "MC7_CE_DATA1", 0x13c, 0 },
|
|
{ "MC7_CE_DATA2", 0x140, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_UE_ADDR", 0x144, 0 },
|
|
{ "MC7_UE_DATA0", 0x148, 0 },
|
|
{ "MC7_UE_DATA1", 0x14c, 0 },
|
|
{ "MC7_UE_DATA2", 0x150, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_ADDR", 0x154, 0 },
|
|
{ "Addr", 3, 29 },
|
|
{ "MC7_BD_DATA0", 0x158, 0 },
|
|
{ "MC7_BD_DATA1", 0x15c, 0 },
|
|
{ "MC7_BD_DATA2", 0x160, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_OP", 0x164, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_BIST_ADDR_BEG", 0x168, 0 },
|
|
{ "AddrBeg", 5, 27 },
|
|
{ "MC7_BIST_ADDR_END", 0x16c, 0 },
|
|
{ "AddrEnd", 5, 27 },
|
|
{ "MC7_BIST_DATA", 0x170, 0 },
|
|
{ "MC7_BIST_OP", 0x174, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Gap", 4, 5 },
|
|
{ "Cont", 3, 1 },
|
|
{ "DataPat", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_INT_ENABLE", 0x178, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ "MC7_INT_CAUSE", 0x17c, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mc7_pmtx_regs[] = {
|
|
{ "MC7_CFG", 0x180, 0 },
|
|
{ "ImpSetUpdate", 14, 1 },
|
|
{ "IFEn", 13, 1 },
|
|
{ "TERM300", 12, 1 },
|
|
{ "TERM150", 11, 1 },
|
|
{ "Slow", 10, 1 },
|
|
{ "Width", 8, 2 },
|
|
{ "ODTEn", 7, 1 },
|
|
{ "Bks", 6, 1 },
|
|
{ "Org", 5, 1 },
|
|
{ "Den", 2, 3 },
|
|
{ "Rdy", 1, 1 },
|
|
{ "ClkEn", 0, 1 },
|
|
{ "MC7_MODE", 0x184, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Mode", 0, 16 },
|
|
{ "MC7_EXT_MODE1", 0x188, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "OCDAdjustMode", 20, 1 },
|
|
{ "OCDCode", 16, 4 },
|
|
{ "ExtMode1", 0, 16 },
|
|
{ "MC7_EXT_MODE2", 0x18c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode2", 0, 16 },
|
|
{ "MC7_EXT_MODE3", 0x190, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode3", 0, 16 },
|
|
{ "MC7_PRE", 0x194, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "MC7_REF", 0x198, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "PreRefDiv", 1, 14 },
|
|
{ "PerRefEn", 0, 1 },
|
|
{ "MC7_DLL", 0x19c, 0 },
|
|
{ "DLLLock", 31, 1 },
|
|
{ "DLLDelta", 24, 7 },
|
|
{ "ManDelta", 3, 7 },
|
|
{ "DLLDeltaSel", 2, 1 },
|
|
{ "DLLEnb", 1, 1 },
|
|
{ "DLLRst", 0, 1 },
|
|
{ "MC7_PARM", 0x1a0, 0 },
|
|
{ "ActToPreDly", 26, 4 },
|
|
{ "ActToRdWrDly", 23, 3 },
|
|
{ "PreCyc", 20, 3 },
|
|
{ "RefCyc", 13, 7 },
|
|
{ "BkCyc", 8, 5 },
|
|
{ "WrToRdDly", 4, 4 },
|
|
{ "RdToWrDly", 0, 4 },
|
|
{ "MC7_HWM_WRR", 0x1a4, 0 },
|
|
{ "MEM_HWM", 26, 6 },
|
|
{ "ULP_HWM", 22, 4 },
|
|
{ "TOT_RLD_WT", 14, 8 },
|
|
{ "MEM_RLD_WT", 7, 7 },
|
|
{ "ULP_RLD_WT", 0, 7 },
|
|
{ "MC7_CAL", 0x1a8, 0 },
|
|
{ "BUSY", 31, 1 },
|
|
{ "CAL_FAULT", 30, 1 },
|
|
{ "PER_CAL_DIV", 22, 8 },
|
|
{ "PER_CAL_EN", 21, 1 },
|
|
{ "SGL_CAL_EN", 20, 1 },
|
|
{ "IMP_UPD_MODE", 19, 1 },
|
|
{ "IMP_SEL", 18, 1 },
|
|
{ "IMP_MAN_PD", 15, 3 },
|
|
{ "IMP_MAN_PU", 12, 3 },
|
|
{ "IMP_CAL_PD", 9, 3 },
|
|
{ "IMP_CAL_PU", 6, 3 },
|
|
{ "IMP_SET_PD", 3, 3 },
|
|
{ "IMP_SET_PU", 0, 3 },
|
|
{ "MC7_ERR_ADDR", 0x1ac, 0 },
|
|
{ "ErrAddress", 3, 29 },
|
|
{ "ErrAgent", 1, 2 },
|
|
{ "ErrOp", 0, 1 },
|
|
{ "MC7_ECC", 0x1b0, 0 },
|
|
{ "UECnt", 10, 8 },
|
|
{ "CECnt", 2, 8 },
|
|
{ "ECCChkEn", 1, 1 },
|
|
{ "ECCGenEn", 0, 1 },
|
|
{ "MC7_CE_ADDR", 0x1b4, 0 },
|
|
{ "MC7_CE_DATA0", 0x1b8, 0 },
|
|
{ "MC7_CE_DATA1", 0x1bc, 0 },
|
|
{ "MC7_CE_DATA2", 0x1c0, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_UE_ADDR", 0x1c4, 0 },
|
|
{ "MC7_UE_DATA0", 0x1c8, 0 },
|
|
{ "MC7_UE_DATA1", 0x1cc, 0 },
|
|
{ "MC7_UE_DATA2", 0x1d0, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_ADDR", 0x1d4, 0 },
|
|
{ "Addr", 3, 29 },
|
|
{ "MC7_BD_DATA0", 0x1d8, 0 },
|
|
{ "MC7_BD_DATA1", 0x1dc, 0 },
|
|
{ "MC7_BD_DATA2", 0x1e0, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_OP", 0x1e4, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_BIST_ADDR_BEG", 0x1e8, 0 },
|
|
{ "AddrBeg", 5, 27 },
|
|
{ "MC7_BIST_ADDR_END", 0x1ec, 0 },
|
|
{ "AddrEnd", 5, 27 },
|
|
{ "MC7_BIST_DATA", 0x1f0, 0 },
|
|
{ "MC7_BIST_OP", 0x1f4, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Gap", 4, 5 },
|
|
{ "Cont", 3, 1 },
|
|
{ "DataPat", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_INT_ENABLE", 0x1f8, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ "MC7_INT_CAUSE", 0x1fc, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mc7_cm_regs[] = {
|
|
{ "MC7_CFG", 0x200, 0 },
|
|
{ "ImpSetUpdate", 14, 1 },
|
|
{ "IFEn", 13, 1 },
|
|
{ "TERM300", 12, 1 },
|
|
{ "TERM150", 11, 1 },
|
|
{ "Slow", 10, 1 },
|
|
{ "Width", 8, 2 },
|
|
{ "ODTEn", 7, 1 },
|
|
{ "Bks", 6, 1 },
|
|
{ "Org", 5, 1 },
|
|
{ "Den", 2, 3 },
|
|
{ "Rdy", 1, 1 },
|
|
{ "ClkEn", 0, 1 },
|
|
{ "MC7_MODE", 0x204, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Mode", 0, 16 },
|
|
{ "MC7_EXT_MODE1", 0x208, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "OCDAdjustMode", 20, 1 },
|
|
{ "OCDCode", 16, 4 },
|
|
{ "ExtMode1", 0, 16 },
|
|
{ "MC7_EXT_MODE2", 0x20c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode2", 0, 16 },
|
|
{ "MC7_EXT_MODE3", 0x210, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "ExtMode3", 0, 16 },
|
|
{ "MC7_PRE", 0x214, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "MC7_REF", 0x218, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "PreRefDiv", 1, 14 },
|
|
{ "PerRefEn", 0, 1 },
|
|
{ "MC7_DLL", 0x21c, 0 },
|
|
{ "DLLLock", 31, 1 },
|
|
{ "DLLDelta", 24, 7 },
|
|
{ "ManDelta", 3, 7 },
|
|
{ "DLLDeltaSel", 2, 1 },
|
|
{ "DLLEnb", 1, 1 },
|
|
{ "DLLRst", 0, 1 },
|
|
{ "MC7_PARM", 0x220, 0 },
|
|
{ "ActToPreDly", 26, 4 },
|
|
{ "ActToRdWrDly", 23, 3 },
|
|
{ "PreCyc", 20, 3 },
|
|
{ "RefCyc", 13, 7 },
|
|
{ "BkCyc", 8, 5 },
|
|
{ "WrToRdDly", 4, 4 },
|
|
{ "RdToWrDly", 0, 4 },
|
|
{ "MC7_HWM_WRR", 0x224, 0 },
|
|
{ "MEM_HWM", 26, 6 },
|
|
{ "ULP_HWM", 22, 4 },
|
|
{ "TOT_RLD_WT", 14, 8 },
|
|
{ "MEM_RLD_WT", 7, 7 },
|
|
{ "ULP_RLD_WT", 0, 7 },
|
|
{ "MC7_CAL", 0x228, 0 },
|
|
{ "BUSY", 31, 1 },
|
|
{ "CAL_FAULT", 30, 1 },
|
|
{ "PER_CAL_DIV", 22, 8 },
|
|
{ "PER_CAL_EN", 21, 1 },
|
|
{ "SGL_CAL_EN", 20, 1 },
|
|
{ "IMP_UPD_MODE", 19, 1 },
|
|
{ "IMP_SEL", 18, 1 },
|
|
{ "IMP_MAN_PD", 15, 3 },
|
|
{ "IMP_MAN_PU", 12, 3 },
|
|
{ "IMP_CAL_PD", 9, 3 },
|
|
{ "IMP_CAL_PU", 6, 3 },
|
|
{ "IMP_SET_PD", 3, 3 },
|
|
{ "IMP_SET_PU", 0, 3 },
|
|
{ "MC7_ERR_ADDR", 0x22c, 0 },
|
|
{ "ErrAddress", 3, 29 },
|
|
{ "ErrAgent", 1, 2 },
|
|
{ "ErrOp", 0, 1 },
|
|
{ "MC7_ECC", 0x230, 0 },
|
|
{ "UECnt", 10, 8 },
|
|
{ "CECnt", 2, 8 },
|
|
{ "ECCChkEn", 1, 1 },
|
|
{ "ECCGenEn", 0, 1 },
|
|
{ "MC7_CE_ADDR", 0x234, 0 },
|
|
{ "MC7_CE_DATA0", 0x238, 0 },
|
|
{ "MC7_CE_DATA1", 0x23c, 0 },
|
|
{ "MC7_CE_DATA2", 0x240, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_UE_ADDR", 0x244, 0 },
|
|
{ "MC7_UE_DATA0", 0x248, 0 },
|
|
{ "MC7_UE_DATA1", 0x24c, 0 },
|
|
{ "MC7_UE_DATA2", 0x250, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_ADDR", 0x254, 0 },
|
|
{ "Addr", 3, 29 },
|
|
{ "MC7_BD_DATA0", 0x258, 0 },
|
|
{ "MC7_BD_DATA1", 0x25c, 0 },
|
|
{ "MC7_BD_DATA2", 0x260, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "MC7_BD_OP", 0x264, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_BIST_ADDR_BEG", 0x268, 0 },
|
|
{ "AddrBeg", 5, 27 },
|
|
{ "MC7_BIST_ADDR_END", 0x26c, 0 },
|
|
{ "AddrEnd", 5, 27 },
|
|
{ "MC7_BIST_DATA", 0x270, 0 },
|
|
{ "MC7_BIST_OP", 0x274, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Gap", 4, 5 },
|
|
{ "Cont", 3, 1 },
|
|
{ "DataPat", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ "MC7_INT_ENABLE", 0x278, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ "MC7_INT_CAUSE", 0x27c, 0 },
|
|
{ "AE", 17, 1 },
|
|
{ "PE", 2, 15 },
|
|
{ "UE", 1, 1 },
|
|
{ "CE", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_cim_regs[] = {
|
|
{ "CIM_BOOT_CFG", 0x280, 0 },
|
|
{ "BootAddr", 2, 30 },
|
|
{ "BootSdram", 1, 1 },
|
|
{ "uPCRst", 0, 1 },
|
|
{ "CIM_FLASH_BASE_ADDR", 0x284, 0 },
|
|
{ "FlashBaseAddr", 2, 22 },
|
|
{ "CIM_FLASH_ADDR_SIZE", 0x288, 0 },
|
|
{ "FlashAddrSize", 2, 22 },
|
|
{ "CIM_SDRAM_BASE_ADDR", 0x28c, 0 },
|
|
{ "SdramBaseAddr", 2, 30 },
|
|
{ "CIM_SDRAM_ADDR_SIZE", 0x290, 0 },
|
|
{ "SdramAddrSize", 2, 30 },
|
|
{ "CIM_UP_SPARE_INT", 0x294, 0 },
|
|
{ "uPSpareInt", 0, 3 },
|
|
{ "CIM_HOST_INT_ENABLE", 0x298, 0 },
|
|
{ "DTagParErr", 28, 1 },
|
|
{ "ITagParErr", 27, 1 },
|
|
{ "IBQTPParErr", 26, 1 },
|
|
{ "IBQULPParErr", 25, 1 },
|
|
{ "IBQSGEHIParErr", 24, 1 },
|
|
{ "IBQSGELOParErr", 23, 1 },
|
|
{ "OBQULPLOParErr", 22, 1 },
|
|
{ "OBQULPHIParErr", 21, 1 },
|
|
{ "OBQSGEParErr", 20, 1 },
|
|
{ "DCacheParErr", 19, 1 },
|
|
{ "ICacheParErr", 18, 1 },
|
|
{ "DRamParErr", 17, 1 },
|
|
{ "Timer1IntEn", 15, 1 },
|
|
{ "Timer0IntEn", 14, 1 },
|
|
{ "PrefDropIntEn", 13, 1 },
|
|
{ "BlkWrPlIntEn", 12, 1 },
|
|
{ "BlkRdPlIntEn", 11, 1 },
|
|
{ "BlkWrCtlIntEn", 10, 1 },
|
|
{ "BlkRdCtlIntEn", 9, 1 },
|
|
{ "BlkWrFlashIntEn", 8, 1 },
|
|
{ "BlkRdFlashIntEn", 7, 1 },
|
|
{ "SglWrFlashIntEn", 6, 1 },
|
|
{ "WrBlkFlashIntEn", 5, 1 },
|
|
{ "BlkWrBootIntEn", 4, 1 },
|
|
{ "BlkRdBootIntEn", 3, 1 },
|
|
{ "FlashRangeIntEn", 2, 1 },
|
|
{ "SdramRangeIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_HOST_INT_CAUSE", 0x29c, 0 },
|
|
{ "DTagParErr", 28, 1 },
|
|
{ "ITagParErr", 27, 1 },
|
|
{ "IBQTPParErr", 26, 1 },
|
|
{ "IBQULPParErr", 25, 1 },
|
|
{ "IBQSGEHIParErr", 24, 1 },
|
|
{ "IBQSGELOParErr", 23, 1 },
|
|
{ "OBQULPLOParErr", 22, 1 },
|
|
{ "OBQULPHIParErr", 21, 1 },
|
|
{ "OBQSGEParErr", 20, 1 },
|
|
{ "DCacheParErr", 19, 1 },
|
|
{ "ICacheParErr", 18, 1 },
|
|
{ "DRamParErr", 17, 1 },
|
|
{ "Timer1Int", 15, 1 },
|
|
{ "Timer0Int", 14, 1 },
|
|
{ "PrefDropInt", 13, 1 },
|
|
{ "BlkWrPlInt", 12, 1 },
|
|
{ "BlkRdPlInt", 11, 1 },
|
|
{ "BlkWrCtlInt", 10, 1 },
|
|
{ "BlkRdCtlInt", 9, 1 },
|
|
{ "BlkWrFlashInt", 8, 1 },
|
|
{ "BlkRdFlashInt", 7, 1 },
|
|
{ "SglWrFlashInt", 6, 1 },
|
|
{ "WrBlkFlashInt", 5, 1 },
|
|
{ "BlkWrBootInt", 4, 1 },
|
|
{ "BlkRdBootInt", 3, 1 },
|
|
{ "FlashRangeInt", 2, 1 },
|
|
{ "SdramRangeInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_UP_INT_ENABLE", 0x2a0, 0 },
|
|
{ "DTagParErr", 28, 1 },
|
|
{ "ITagParErr", 27, 1 },
|
|
{ "IBQTPParErr", 26, 1 },
|
|
{ "IBQULPParErr", 25, 1 },
|
|
{ "IBQSGEHIParErr", 24, 1 },
|
|
{ "IBQSGELOParErr", 23, 1 },
|
|
{ "OBQULPLOParErr", 22, 1 },
|
|
{ "OBQULPHIParErr", 21, 1 },
|
|
{ "OBQSGEParErr", 20, 1 },
|
|
{ "DCacheParErr", 19, 1 },
|
|
{ "ICacheParErr", 18, 1 },
|
|
{ "DRamParErr", 17, 1 },
|
|
{ "MstPlIntEn", 16, 1 },
|
|
{ "Timer1IntEn", 15, 1 },
|
|
{ "Timer0IntEn", 14, 1 },
|
|
{ "PrefDropIntEn", 13, 1 },
|
|
{ "BlkWrPlIntEn", 12, 1 },
|
|
{ "BlkRdPlIntEn", 11, 1 },
|
|
{ "BlkWrCtlIntEn", 10, 1 },
|
|
{ "BlkRdCtlIntEn", 9, 1 },
|
|
{ "BlkWrFlashIntEn", 8, 1 },
|
|
{ "BlkRdFlashIntEn", 7, 1 },
|
|
{ "SglWrFlashIntEn", 6, 1 },
|
|
{ "WrBlkFlashIntEn", 5, 1 },
|
|
{ "BlkWrBootIntEn", 4, 1 },
|
|
{ "BlkRdBootIntEn", 3, 1 },
|
|
{ "FlashRangeIntEn", 2, 1 },
|
|
{ "SdramRangeIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_UP_INT_CAUSE", 0x2a4, 0 },
|
|
{ "DTagParErr", 28, 1 },
|
|
{ "ITagParErr", 27, 1 },
|
|
{ "IBQTPParErr", 26, 1 },
|
|
{ "IBQULPParErr", 25, 1 },
|
|
{ "IBQSGEHIParErr", 24, 1 },
|
|
{ "IBQSGELOParErr", 23, 1 },
|
|
{ "OBQULPLOParErr", 22, 1 },
|
|
{ "OBQULPHIParErr", 21, 1 },
|
|
{ "OBQSGEParErr", 20, 1 },
|
|
{ "DCacheParErr", 19, 1 },
|
|
{ "ICacheParErr", 18, 1 },
|
|
{ "DRamParErr", 17, 1 },
|
|
{ "MstPlInt", 16, 1 },
|
|
{ "Timer1Int", 15, 1 },
|
|
{ "Timer0Int", 14, 1 },
|
|
{ "PrefDropInt", 13, 1 },
|
|
{ "BlkWrPlInt", 12, 1 },
|
|
{ "BlkRdPlInt", 11, 1 },
|
|
{ "BlkWrCtlInt", 10, 1 },
|
|
{ "BlkRdCtlInt", 9, 1 },
|
|
{ "BlkWrFlashInt", 8, 1 },
|
|
{ "BlkRdFlashInt", 7, 1 },
|
|
{ "SglWrFlashInt", 6, 1 },
|
|
{ "WrBlkFlashInt", 5, 1 },
|
|
{ "BlkWrBootInt", 4, 1 },
|
|
{ "BlkRdBootInt", 3, 1 },
|
|
{ "FlashRangeInt", 2, 1 },
|
|
{ "SdramRangeInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_IBQ_FULLA_THRSH", 0x2a8, 0 },
|
|
{ "Ibq0FullThrsh", 0, 9 },
|
|
{ "Ibq1FullThrsh", 16, 9 },
|
|
{ "CIM_IBQ_FULLB_THRSH", 0x2ac, 0 },
|
|
{ "Ibq2FullThrsh", 0, 9 },
|
|
{ "Ibq3FullThrsh", 16, 9 },
|
|
{ "CIM_HOST_ACC_CTRL", 0x2b0, 0 },
|
|
{ "HostBusy", 17, 1 },
|
|
{ "HostWrite", 16, 1 },
|
|
{ "HostAddr", 0, 16 },
|
|
{ "CIM_HOST_ACC_DATA", 0x2b4, 0 },
|
|
{ "CIM_IBQ_DBG_CFG", 0x2c0, 0 },
|
|
{ "IbqDbgAddr", 16, 9 },
|
|
{ "IbqDbgQID", 3, 2 },
|
|
{ "IbqDbgWr", 2, 1 },
|
|
{ "IbqDbgBusy", 1, 1 },
|
|
{ "IbqDbgEn", 0, 1 },
|
|
{ "CIM_OBQ_DBG_CFG", 0x2c4, 0 },
|
|
{ "ObqDbgAddr", 16, 9 },
|
|
{ "ObqDbgQID", 3, 2 },
|
|
{ "ObqDbgWr", 2, 1 },
|
|
{ "ObqDbgBusy", 1, 1 },
|
|
{ "ObqDbgEn", 0, 1 },
|
|
{ "CIM_IBQ_DBG_DATA", 0x2c8, 0 },
|
|
{ "CIM_OBQ_DBG_DATA", 0x2cc, 0 },
|
|
{ "CIM_CDEBUGDATA", 0x2d0, 0 },
|
|
{ "CDebugDataH", 16, 16 },
|
|
{ "CDebugDataL", 0, 16 },
|
|
{ "CIM_DEBUGCFG", 0x2e0, 0 },
|
|
{ "POLADbgRdPtr", 23, 9 },
|
|
{ "PILADbgRdPtr", 14, 9 },
|
|
{ "LADbgEn", 12, 1 },
|
|
{ "DebugSelH", 5, 5 },
|
|
{ "DebugSelL", 0, 5 },
|
|
{ "CIM_DEBUGSTS", 0x2e4, 0 },
|
|
{ "POLADbgWrPtr", 16, 9 },
|
|
{ "PILADbgWrPtr", 0, 9 },
|
|
{ "CIM_PO_LA_DEBUGDATA", 0x2e8, 0 },
|
|
{ "CIM_PI_LA_DEBUGDATA", 0x2ec, 0 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_tp1_regs[] = {
|
|
{ "TP_IN_CONFIG", 0x300, 0 },
|
|
{ "RXFbArbPrio", 25, 1 },
|
|
{ "TXFbArbPrio", 24, 1 },
|
|
{ "DBMaxOpCnt", 16, 8 },
|
|
{ "IPv6Enable", 15, 1 },
|
|
{ "NICMode", 14, 1 },
|
|
{ "EChecksumCheckTCP", 13, 1 },
|
|
{ "EChecksumCheckIP", 12, 1 },
|
|
{ "ECPL", 10, 1 },
|
|
{ "EEthernet", 8, 1 },
|
|
{ "ETunnel", 7, 1 },
|
|
{ "CChecksumCheckTCP", 6, 1 },
|
|
{ "CChecksumCheckIP", 5, 1 },
|
|
{ "CCPL", 3, 1 },
|
|
{ "CEthernet", 1, 1 },
|
|
{ "CTunnel", 0, 1 },
|
|
{ "TP_OUT_CONFIG", 0x304, 0 },
|
|
{ "IPIDSplitMode", 16, 1 },
|
|
{ "VLANExtractionEnable2ndPort", 13, 1 },
|
|
{ "VLANExtractionEnable", 12, 1 },
|
|
{ "EChecksumGenerateTCP", 11, 1 },
|
|
{ "EChecksumGenerateIP", 10, 1 },
|
|
{ "ECPL", 8, 1 },
|
|
{ "EEthernet", 6, 1 },
|
|
{ "CChecksumGenerateTCP", 5, 1 },
|
|
{ "CChecksumGenerateIP", 4, 1 },
|
|
{ "CCPL", 2, 1 },
|
|
{ "CEthernet", 0, 1 },
|
|
{ "TP_GLOBAL_CONFIG", 0x308, 0 },
|
|
{ "SYNCookieParams", 26, 6 },
|
|
{ "RXFlowControlDisable", 25, 1 },
|
|
{ "TXPacingEnable", 24, 1 },
|
|
{ "AttackFilterEnable", 23, 1 },
|
|
{ "SYNCookieNoOptions", 22, 1 },
|
|
{ "ProtectedMode", 21, 1 },
|
|
{ "PingDrop", 20, 1 },
|
|
{ "FragmentDrop", 19, 1 },
|
|
{ "FiveTupleLookup", 17, 2 },
|
|
{ "PathMTU", 15, 1 },
|
|
{ "IPIdentSplit", 14, 1 },
|
|
{ "IPChecksumOffload", 13, 1 },
|
|
{ "UDPChecksumOffload", 12, 1 },
|
|
{ "TCPChecksumOffload", 11, 1 },
|
|
{ "QOSMapping", 10, 1 },
|
|
{ "TCAMServerUse", 8, 2 },
|
|
{ "IPTTL", 0, 8 },
|
|
{ "TP_GLOBAL_RX_CREDIT", 0x30c, 0 },
|
|
{ "TP_CMM_SIZE", 0x310, 0 },
|
|
{ "CMMemMgrSize", 0, 28 },
|
|
{ "TP_CMM_MM_BASE", 0x314, 0 },
|
|
{ "CMMemMgrBase", 0, 28 },
|
|
{ "TP_CMM_TIMER_BASE", 0x318, 0 },
|
|
{ "CMTimerMaxNum", 28, 2 },
|
|
{ "CMTimerBase", 0, 28 },
|
|
{ "TP_PMM_SIZE", 0x31c, 0 },
|
|
{ "PMSize", 0, 28 },
|
|
{ "TP_PMM_TX_BASE", 0x320, 0 },
|
|
{ "TP_PMM_DEFRAG_BASE", 0x324, 0 },
|
|
{ "TP_PMM_RX_BASE", 0x328, 0 },
|
|
{ "TP_PMM_RX_PAGE_SIZE", 0x32c, 0 },
|
|
{ "TP_PMM_RX_MAX_PAGE", 0x330, 0 },
|
|
{ "PMRxMaxPage", 0, 21 },
|
|
{ "TP_PMM_TX_PAGE_SIZE", 0x334, 0 },
|
|
{ "TP_PMM_TX_MAX_PAGE", 0x338, 0 },
|
|
{ "PMTxMaxPage", 0, 21 },
|
|
{ "TP_TCP_OPTIONS", 0x340, 0 },
|
|
{ "MTUDefault", 16, 16 },
|
|
{ "MTUEnable", 10, 1 },
|
|
{ "SACKTx", 9, 1 },
|
|
{ "SACKRx", 8, 1 },
|
|
{ "SACKMode", 4, 2 },
|
|
{ "WindowScaleMode", 2, 2 },
|
|
{ "TimestampsMode", 0, 2 },
|
|
{ "TP_DACK_CONFIG", 0x344, 0 },
|
|
{ "AutoState3", 30, 2 },
|
|
{ "AutoState2", 28, 2 },
|
|
{ "AutoState1", 26, 2 },
|
|
{ "ByteThreshold", 5, 20 },
|
|
{ "MSSThreshold", 3, 2 },
|
|
{ "AutoCareful", 2, 1 },
|
|
{ "AutoEnable", 1, 1 },
|
|
{ "Mode", 0, 1 },
|
|
{ "TP_PC_CONFIG", 0x348, 0 },
|
|
{ "CMCacheDisable", 31, 1 },
|
|
{ "EnableOcspiFull", 30, 1 },
|
|
{ "EnableFLMErrorDDP", 29, 1 },
|
|
{ "LockTid", 28, 1 },
|
|
{ "FixRcvWnd", 27, 1 },
|
|
{ "TxTosQueueMapMode", 26, 1 },
|
|
{ "RddpCongEn", 25, 1 },
|
|
{ "EnableOnFlyPDU", 24, 1 },
|
|
{ "EnableEPCMDAFull", 23, 1 },
|
|
{ "ModulateUnionMode", 22, 1 },
|
|
{ "TxDataAckRateEnable", 21, 1 },
|
|
{ "TxDeferEnable", 20, 1 },
|
|
{ "RxCongestionMode", 19, 1 },
|
|
{ "HearbeatOnceDACK", 18, 1 },
|
|
{ "HearbeatOnceHeap", 17, 1 },
|
|
{ "HearbeatDACK", 16, 1 },
|
|
{ "TxCongestionMode", 15, 1 },
|
|
{ "AcceptLatestRcvAdv", 14, 1 },
|
|
{ "DisableSYNData", 13, 1 },
|
|
{ "DisableWindowPSH", 12, 1 },
|
|
{ "DisableFINOldData", 11, 1 },
|
|
{ "EnableFLMError", 10, 1 },
|
|
{ "DisableNextMtu", 9, 1 },
|
|
{ "FilterPeerFIN", 8, 1 },
|
|
{ "EnableFeedbackSend", 7, 1 },
|
|
{ "EnableRDMAError", 6, 1 },
|
|
{ "EnableDDPFlowControl", 5, 1 },
|
|
{ "DisableHeldFIN", 4, 1 },
|
|
{ "TableLatencyDelta", 0, 4 },
|
|
{ "TP_PC_CONFIG2", 0x34c, 0 },
|
|
{ "DisbleDaParbit0", 15, 1 },
|
|
{ "EnableArpMiss", 13, 1 },
|
|
{ "EnableNonOfdTnlSyn", 12, 1 },
|
|
{ "EnableIPv6RSS", 11, 1 },
|
|
{ "EnableDropRQEmptyPkt", 10, 1 },
|
|
{ "EnableTxPortfromDA2", 9, 1 },
|
|
{ "EnableRxPktTmstpRss", 8, 1 },
|
|
{ "EnableSndUnaInRxData", 7, 1 },
|
|
{ "EnableRxPortFromAddr", 6, 1 },
|
|
{ "EnableTxPortfromDA", 5, 1 },
|
|
{ "EnableCHdrAFull", 4, 1 },
|
|
{ "EnableNonOfdScbBit", 3, 1 },
|
|
{ "EnableNonOfdTidRss", 2, 1 },
|
|
{ "EnableNonOfdTcbRss", 1, 1 },
|
|
{ "EnableOldRxForward", 0, 1 },
|
|
{ "TP_TCP_BACKOFF_REG0", 0x350, 0 },
|
|
{ "TimerBackoffIndex3", 24, 8 },
|
|
{ "TimerBackoffIndex2", 16, 8 },
|
|
{ "TimerBackoffIndex1", 8, 8 },
|
|
{ "TimerBackoffIndex0", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG1", 0x354, 0 },
|
|
{ "TimerBackoffIndex7", 24, 8 },
|
|
{ "TimerBackoffIndex6", 16, 8 },
|
|
{ "TimerBackoffIndex5", 8, 8 },
|
|
{ "TimerBackoffIndex4", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG2", 0x358, 0 },
|
|
{ "TimerBackoffIndex11", 24, 8 },
|
|
{ "TimerBackoffIndex10", 16, 8 },
|
|
{ "TimerBackoffIndex9", 8, 8 },
|
|
{ "TimerBackoffIndex8", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG3", 0x35c, 0 },
|
|
{ "TimerBackoffIndex15", 24, 8 },
|
|
{ "TimerBackoffIndex14", 16, 8 },
|
|
{ "TimerBackoffIndex13", 8, 8 },
|
|
{ "TimerBackoffIndex12", 0, 8 },
|
|
{ "TP_PARA_REG0", 0x360, 0 },
|
|
{ "InitCwnd", 24, 3 },
|
|
{ "DupAckThresh", 20, 4 },
|
|
{ "TP_PARA_REG1", 0x364, 0 },
|
|
{ "InitRwnd", 16, 16 },
|
|
{ "InitialSSThresh", 0, 16 },
|
|
{ "TP_PARA_REG2", 0x368, 0 },
|
|
{ "MaxRxData", 16, 16 },
|
|
{ "RxCoalesceSize", 0, 16 },
|
|
{ "TP_PARA_REG3", 0x36c, 0 },
|
|
{ "TunnelCngDrop1", 21, 1 },
|
|
{ "TunnelCngDrop0", 20, 1 },
|
|
{ "TxDataAckIdx", 16, 4 },
|
|
{ "RxFragEnable", 12, 3 },
|
|
{ "TxPaceFixedStrict", 11, 1 },
|
|
{ "TxPaceAutoStrict", 10, 1 },
|
|
{ "TxPaceFixed", 9, 1 },
|
|
{ "TxPaceAuto", 8, 1 },
|
|
{ "RxUrgTunnel", 6, 1 },
|
|
{ "RxUrgMode", 5, 1 },
|
|
{ "TxUrgMode", 4, 1 },
|
|
{ "CngCtrlMode", 2, 2 },
|
|
{ "RxCoalesceEnable", 1, 1 },
|
|
{ "RxCoalescePshEn", 0, 1 },
|
|
{ "TP_PARA_REG4", 0x370, 0 },
|
|
{ "HighSpeedCfg", 24, 8 },
|
|
{ "NewRenoCfg", 16, 8 },
|
|
{ "TahoeCfg", 8, 8 },
|
|
{ "RenoCfg", 0, 8 },
|
|
{ "TP_PARA_REG5", 0x374, 0 },
|
|
{ "IndicateSize", 16, 16 },
|
|
{ "SchdEnable", 8, 1 },
|
|
{ "RxDdpOffInit", 3, 1 },
|
|
{ "OnFlyDDPEnable", 2, 1 },
|
|
{ "DackTimerSpin", 1, 1 },
|
|
{ "PushTimerEnable", 0, 1 },
|
|
{ "TP_PARA_REG6", 0x378, 0 },
|
|
{ "TxPDUSizeAdj", 16, 8 },
|
|
{ "EnableDeferACK", 12, 1 },
|
|
{ "EnableESnd", 11, 1 },
|
|
{ "EnableCSnd", 10, 1 },
|
|
{ "EnablePDUE", 9, 1 },
|
|
{ "EnablePDUC", 8, 1 },
|
|
{ "EnableBUFI", 7, 1 },
|
|
{ "EnableBUFE", 6, 1 },
|
|
{ "EnableDefer", 5, 1 },
|
|
{ "EnableClearRxmtOos", 4, 1 },
|
|
{ "DisablePDUCng", 3, 1 },
|
|
{ "DisablePDUTimeout", 2, 1 },
|
|
{ "DisablePDURxmt", 1, 1 },
|
|
{ "DisablePDUxmt", 0, 1 },
|
|
{ "TP_PARA_REG7", 0x37c, 0 },
|
|
{ "PMMaxXferLen1", 16, 16 },
|
|
{ "PMMaxXferLen0", 0, 16 },
|
|
{ "TP_TIMER_RESOLUTION", 0x390, 0 },
|
|
{ "TimerResolution", 16, 8 },
|
|
{ "TimestampResolution", 8, 8 },
|
|
{ "DelayedACKResolution", 0, 8 },
|
|
{ "TP_MSL", 0x394, 0 },
|
|
{ "MSL", 0, 30 },
|
|
{ "TP_RXT_MIN", 0x398, 0 },
|
|
{ "RxtMin", 0, 30 },
|
|
{ "TP_RXT_MAX", 0x39c, 0 },
|
|
{ "RxtMax", 0, 30 },
|
|
{ "TP_PERS_MIN", 0x3a0, 0 },
|
|
{ "PersMin", 0, 30 },
|
|
{ "TP_PERS_MAX", 0x3a4, 0 },
|
|
{ "PersMax", 0, 30 },
|
|
{ "TP_KEEP_IDLE", 0x3a8, 0 },
|
|
{ "KeepaliveIdle", 0, 30 },
|
|
{ "TP_KEEP_INTVL", 0x3ac, 0 },
|
|
{ "KeepaliveIntvl", 0, 30 },
|
|
{ "TP_INIT_SRTT", 0x3b0, 0 },
|
|
{ "InitSrtt", 0, 16 },
|
|
{ "TP_DACK_TIMER", 0x3b4, 0 },
|
|
{ "DackTime", 0, 12 },
|
|
{ "TP_FINWAIT2_TIMER", 0x3b8, 0 },
|
|
{ "Finwait2Time", 0, 30 },
|
|
{ "TP_FAST_FINWAIT2_TIMER", 0x3bc, 0 },
|
|
{ "FastFinwait2Time", 0, 30 },
|
|
{ "TP_SHIFT_CNT", 0x3c0, 0 },
|
|
{ "SynShiftMax", 24, 8 },
|
|
{ "RxtShiftMaxR1", 20, 4 },
|
|
{ "RxtShiftMaxR2", 16, 4 },
|
|
{ "PerShiftBackoffMax", 12, 4 },
|
|
{ "PerShiftMax", 8, 4 },
|
|
{ "KeepaliveMax", 0, 8 },
|
|
{ "TP_TIME_HI", 0x3c8, 0 },
|
|
{ "TP_TIME_LO", 0x3cc, 0 },
|
|
{ "TP_MTU_PORT_TABLE", 0x3d0, 0 },
|
|
{ "Port1MTUValue", 16, 16 },
|
|
{ "Port0MTUValue", 0, 16 },
|
|
{ "TP_ULP_TABLE", 0x3d4, 0 },
|
|
{ "ULPType7Field", 28, 4 },
|
|
{ "ULPType6Field", 24, 4 },
|
|
{ "ULPType5Field", 20, 4 },
|
|
{ "ULPType4Field", 16, 4 },
|
|
{ "ULPType3Field", 12, 4 },
|
|
{ "ULPType2Field", 8, 4 },
|
|
{ "ULPType1Field", 4, 4 },
|
|
{ "ULPType0Field", 0, 4 },
|
|
{ "TP_PACE_TABLE", 0x3d8, 0 },
|
|
{ "TP_CCTRL_TABLE", 0x3dc, 0 },
|
|
{ "TP_TOS_TABLE", 0x3e0, 0 },
|
|
{ "TP_MTU_TABLE", 0x3e4, 0 },
|
|
{ "TP_RSS_MAP_TABLE", 0x3e8, 0 },
|
|
{ "TP_RSS_LKP_TABLE", 0x3ec, 0 },
|
|
{ "TP_RSS_CONFIG", 0x3f0, 0 },
|
|
{ "TNL4tupEn", 29, 1 },
|
|
{ "TNL2tupEn", 28, 1 },
|
|
{ "TNLprtEn", 26, 1 },
|
|
{ "TNLMapEn", 25, 1 },
|
|
{ "TNLLkpEn", 24, 1 },
|
|
{ "OFD4tupEn", 21, 1 },
|
|
{ "OFD2tupEn", 20, 1 },
|
|
{ "OFDMapEn", 17, 1 },
|
|
{ "OFDLkpEn", 16, 1 },
|
|
{ "SYN4tupEn", 13, 1 },
|
|
{ "SYN2tupEn", 12, 1 },
|
|
{ "SYNMapEn", 9, 1 },
|
|
{ "SYNLkpEn", 8, 1 },
|
|
{ "RRCPLMapEn", 7, 1 },
|
|
{ "RRCPLCPUSIZE", 4, 3 },
|
|
{ "RQFeedbackEnable", 3, 1 },
|
|
{ "HashToeplitz", 2, 1 },
|
|
{ "HashSave", 1, 1 },
|
|
{ "Disable", 0, 1 },
|
|
{ "TP_RSS_CONFIG_TNL", 0x3f4, 0 },
|
|
{ "MaskSize", 28, 3 },
|
|
{ "DefaultCPUBase", 22, 6 },
|
|
{ "DefaultCPU", 16, 6 },
|
|
{ "DefaultQueue", 0, 16 },
|
|
{ "TP_RSS_CONFIG_OFD", 0x3f8, 0 },
|
|
{ "MaskSize", 28, 3 },
|
|
{ "DefaultCPUBase", 22, 6 },
|
|
{ "DefaultCPU", 16, 6 },
|
|
{ "DefaultQueue", 0, 16 },
|
|
{ "TP_RSS_CONFIG_SYN", 0x3fc, 0 },
|
|
{ "MaskSize", 28, 3 },
|
|
{ "DefaultCPUBase", 22, 6 },
|
|
{ "DefaultCPU", 16, 6 },
|
|
{ "DefaultQueue", 0, 16 },
|
|
{ "TP_RSS_SECRET_KEY0", 0x400, 0 },
|
|
{ "TP_RSS_SECRET_KEY1", 0x404, 0 },
|
|
{ "TP_RSS_SECRET_KEY2", 0x408, 0 },
|
|
{ "TP_RSS_SECRET_KEY3", 0x40c, 0 },
|
|
{ "TP_TM_PIO_ADDR", 0x418, 0 },
|
|
{ "TP_TM_PIO_DATA", 0x41c, 0 },
|
|
{ "TP_TX_MOD_QUE_TABLE", 0x420, 0 },
|
|
{ "TP_TX_RESOURCE_LIMIT", 0x424, 0 },
|
|
{ "TX_RESOURCE_LIMIT_CH1_PC", 24, 8 },
|
|
{ "TX_RESOURCE_LIMIT_CH1_NON_PC", 16, 8 },
|
|
{ "TX_RESOURCE_LIMIT_CH0_PC", 8, 8 },
|
|
{ "TX_RESOURCE_LIMIT_CH0_NON_PC", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x428, 0 },
|
|
{ "RX_MOD_WEIGHT", 24, 8 },
|
|
{ "TX_MOD_WEIGHT", 16, 8 },
|
|
{ "TX_MOD_TIMER_MODE", 8, 8 },
|
|
{ "TX_MOD_QUEUE_REQ_MAP", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x42c, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x430, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
|
|
{ "TP_MOD_CHANNEL_WEIGHT", 0x434, 0 },
|
|
{ "RX_MOD_CHANNEL_WEIGHT1", 24, 8 },
|
|
{ "RX_MOD_CHANNEL_WEIGHT0", 16, 8 },
|
|
{ "TX_MOD_CHANNEL_WEIGHT1", 8, 8 },
|
|
{ "TX_MOD_CHANNEL_WEIGHT0", 0, 8 },
|
|
{ "TP_MOD_RATE_LIMIT", 0x438, 0 },
|
|
{ "RX_MOD_RATE_LIMIT_INC", 24, 8 },
|
|
{ "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_INC", 8, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
|
|
{ "TP_PIO_ADDR", 0x440, 0 },
|
|
{ "TP_PIO_DATA", 0x444, 0 },
|
|
{ "TP_RESET", 0x44c, 0 },
|
|
{ "FlstInitEnable", 1, 1 },
|
|
{ "TPReset", 0, 1 },
|
|
{ "TP_MIB_INDEX", 0x450, 0 },
|
|
{ "TP_MIB_RDATA", 0x454, 0 },
|
|
{ "TP_SYNC_TIME_HI", 0x458, 0 },
|
|
{ "TP_SYNC_TIME_LO", 0x45c, 0 },
|
|
{ "TP_CMM_MM_RX_FLST_BASE", 0x460, 0 },
|
|
{ "CMRxFlstBase", 0, 28 },
|
|
{ "TP_CMM_MM_TX_FLST_BASE", 0x464, 0 },
|
|
{ "CMTxFlstBase", 0, 28 },
|
|
{ "TP_CMM_MM_PS_FLST_BASE", 0x468, 0 },
|
|
{ "CMPsFlstBase", 0, 28 },
|
|
{ "TP_CMM_MM_MAX_PSTRUCT", 0x46c, 0 },
|
|
{ "CMMaxPstruct", 0, 21 },
|
|
{ "TP_INT_ENABLE", 0x470, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "FlmRxFlstEmpty", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutTcpFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "CTpInTcpFifoPerr", 2, 1 },
|
|
{ "CTpInIpFifoPerr", 1, 1 },
|
|
{ "CTpInEthFifoPerr", 0, 1 },
|
|
{ "TP_INT_CAUSE", 0x474, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "FlmRxFlstEmpty", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutTcpFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "CTpInTcpFifoPerr", 2, 1 },
|
|
{ "CTpInIpFifoPerr", 1, 1 },
|
|
{ "CTpInEthFifoPerr", 0, 1 },
|
|
{ "TP_FLM_FREE_PS_CNT", 0x480, 0 },
|
|
{ "FreePstructCount", 0, 21 },
|
|
{ "TP_FLM_FREE_RX_CNT", 0x484, 0 },
|
|
{ "FreeRxPageCount", 0, 21 },
|
|
{ "TP_FLM_FREE_TX_CNT", 0x488, 0 },
|
|
{ "FreeTxPageCount", 0, 21 },
|
|
{ "TP_TM_HEAP_PUSH_CNT", 0x48c, 0 },
|
|
{ "TP_TM_HEAP_POP_CNT", 0x490, 0 },
|
|
{ "TP_TM_DACK_PUSH_CNT", 0x494, 0 },
|
|
{ "TP_TM_DACK_POP_CNT", 0x498, 0 },
|
|
{ "TP_TM_MOD_PUSH_CNT", 0x49c, 0 },
|
|
{ "TP_MOD_POP_CNT", 0x4a0, 0 },
|
|
{ "TP_TIMER_SEPARATOR", 0x4a4, 0 },
|
|
{ "TP_DEBUG_SEL", 0x4a8, 0 },
|
|
{ "TP_DEBUG_FLAGS", 0x4ac, 0 },
|
|
{ "RxTimerDackFirst", 26, 1 },
|
|
{ "RxTimerDack", 25, 1 },
|
|
{ "RxTimerHeartbeat", 24, 1 },
|
|
{ "RxPawsDrop", 23, 1 },
|
|
{ "RxUrgDataDrop", 22, 1 },
|
|
{ "RxFutureData", 21, 1 },
|
|
{ "RxRcvRxmData", 20, 1 },
|
|
{ "RxRcvOooDataFin", 19, 1 },
|
|
{ "RxRcvOooData", 18, 1 },
|
|
{ "RxRcvWndZero", 17, 1 },
|
|
{ "RxRcvWndLtMss", 16, 1 },
|
|
{ "TxDupAckInc", 11, 1 },
|
|
{ "TxRxmUrg", 10, 1 },
|
|
{ "TxRxmFin", 9, 1 },
|
|
{ "TxRxmSyn", 8, 1 },
|
|
{ "TxRxmNewReno", 7, 1 },
|
|
{ "TxRxmFast", 6, 1 },
|
|
{ "TxRxmTimer", 5, 1 },
|
|
{ "TxRxmTimerKeepalive", 4, 1 },
|
|
{ "TxRxmTimerPersist", 3, 1 },
|
|
{ "TxRcvAdvShrunk", 2, 1 },
|
|
{ "TxRcvAdvZero", 1, 1 },
|
|
{ "TxRcvAdvLtMss", 0, 1 },
|
|
{ "TP_PROXY_FLOW_CNTL", 0x4b0, 0 },
|
|
{ "TP_PC_CONGESTION_CNTL", 0x4b4, 0 },
|
|
{ "EDropTunnel", 19, 1 },
|
|
{ "CDropTunnel", 18, 1 },
|
|
{ "EThreshold", 12, 6 },
|
|
{ "CThreshold", 6, 6 },
|
|
{ "TxThreshold", 0, 6 },
|
|
{ "TP_TX_DROP_COUNT", 0x4bc, 0 },
|
|
{ "TP_CLEAR_DEBUG", 0x4c0, 0 },
|
|
{ "ClrDebug", 0, 1 },
|
|
{ "TP_DEBUG_VEC", 0x4c4, 0 },
|
|
{ "TP_DEBUG_VEC2", 0x4c8, 0 },
|
|
{ "TP_DEBUG_REG_SEL", 0x4cc, 0 },
|
|
{ "TP_DEBUG", 0x4d0, 0 },
|
|
{ "TP_DBG_LA_CONFIG", 0x4d4, 0 },
|
|
{ "TP_DBG_LA_DATAH", 0x4d8, 0 },
|
|
{ "TP_DBG_LA_DATAL", 0x4dc, 0 },
|
|
{ "TP_EMBED_OP_FIELD0", 0x4e8, 0 },
|
|
{ "TP_EMBED_OP_FIELD1", 0x4ec, 0 },
|
|
{ "TP_EMBED_OP_FIELD2", 0x4f0, 0 },
|
|
{ "TP_EMBED_OP_FIELD3", 0x4f4, 0 },
|
|
{ "TP_EMBED_OP_FIELD4", 0x4f8, 0 },
|
|
{ "TP_EMBED_OP_FIELD5", 0x4fc, 0 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_ulp2_rx_regs[] = {
|
|
{ "ULPRX_CTL", 0x500, 0 },
|
|
{ "PCMD1Threshold", 24, 8 },
|
|
{ "PCMD0Threshold", 16, 8 },
|
|
{ "round_robin", 4, 1 },
|
|
{ "RDMA_permissive_mode", 3, 1 },
|
|
{ "PagePodME", 2, 1 },
|
|
{ "IscsiTagTcb", 1, 1 },
|
|
{ "TddpTagTcb", 0, 1 },
|
|
{ "ULPRX_INT_ENABLE", 0x504, 0 },
|
|
{ "DataSelFrameErr0", 7, 1 },
|
|
{ "DataSelFrameErr1", 6, 1 },
|
|
{ "PcmdMuxPerr", 5, 1 },
|
|
{ "ArbFPerr", 4, 1 },
|
|
{ "ArbPF0Perr", 3, 1 },
|
|
{ "ArbPF1Perr", 2, 1 },
|
|
{ "ParErrPcmd", 1, 1 },
|
|
{ "ParErrData", 0, 1 },
|
|
{ "ULPRX_INT_CAUSE", 0x508, 0 },
|
|
{ "DataSelFrameErr0", 7, 1 },
|
|
{ "DataSelFrameErr1", 6, 1 },
|
|
{ "PcmdMuxPerr", 5, 1 },
|
|
{ "ArbFPerr", 4, 1 },
|
|
{ "ArbPF0Perr", 3, 1 },
|
|
{ "ArbPF1Perr", 2, 1 },
|
|
{ "ParErrPcmd", 1, 1 },
|
|
{ "ParErrData", 0, 1 },
|
|
{ "ULPRX_ISCSI_LLIMIT", 0x50c, 0 },
|
|
{ "IscsiLlimit", 6, 26 },
|
|
{ "ULPRX_ISCSI_ULIMIT", 0x510, 0 },
|
|
{ "IscsiUlimit", 6, 26 },
|
|
{ "ULPRX_ISCSI_TAGMASK", 0x514, 0 },
|
|
{ "IscsiTagMask", 6, 26 },
|
|
{ "ULPRX_ISCSI_PSZ", 0x518, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULPRX_TDDP_LLIMIT", 0x51c, 0 },
|
|
{ "TddpLlimit", 6, 26 },
|
|
{ "ULPRX_TDDP_ULIMIT", 0x520, 0 },
|
|
{ "TddpUlimit", 6, 26 },
|
|
{ "ULPRX_TDDP_TAGMASK", 0x524, 0 },
|
|
{ "TddpTagMask", 6, 26 },
|
|
{ "ULPRX_TDDP_PSZ", 0x528, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULPRX_STAG_LLIMIT", 0x52c, 0 },
|
|
{ "ULPRX_STAG_ULIMIT", 0x530, 0 },
|
|
{ "ULPRX_RQ_LLIMIT", 0x534, 0 },
|
|
{ "ULPRX_RQ_ULIMIT", 0x538, 0 },
|
|
{ "ULPRX_PBL_LLIMIT", 0x53c, 0 },
|
|
{ "ULPRX_PBL_ULIMIT", 0x540, 0 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_ulp2_tx_regs[] = {
|
|
{ "ULPTX_CONFIG", 0x580, 0 },
|
|
{ "CFG_CQE_SOP_MASK", 1, 1 },
|
|
{ "CFG_RR_ARB", 0, 1 },
|
|
{ "ULPTX_INT_ENABLE", 0x584, 0 },
|
|
{ "cmd_fifo_perr_set1", 7, 1 },
|
|
{ "cmd_fifo_perr_set0", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "imm_data_perr_set_ch1", 3, 1 },
|
|
{ "imm_data_perr_set_ch0", 2, 1 },
|
|
{ "Pbl_bound_err_ch1", 1, 1 },
|
|
{ "Pbl_bound_err_ch0", 0, 1 },
|
|
{ "ULPTX_INT_CAUSE", 0x588, 0 },
|
|
{ "cmd_fifo_perr_set1", 7, 1 },
|
|
{ "cmd_fifo_perr_set0", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "imm_data_perr_set_ch1", 3, 1 },
|
|
{ "imm_data_perr_set_ch0", 2, 1 },
|
|
{ "Pbl_bound_err_ch1", 1, 1 },
|
|
{ "Pbl_bound_err_ch0", 0, 1 },
|
|
{ "ULPTX_TPT_LLIMIT", 0x58c, 0 },
|
|
{ "ULPTX_TPT_ULIMIT", 0x590, 0 },
|
|
{ "ULPTX_PBL_LLIMIT", 0x594, 0 },
|
|
{ "ULPTX_PBL_ULIMIT", 0x598, 0 },
|
|
{ "ULPTX_CPL_ERR_OFFSET", 0x59c, 0 },
|
|
{ "ULPTX_CPL_ERR_MASK", 0x5a0, 0 },
|
|
{ "ULPTX_CPL_ERR_VALUE", 0x5a4, 0 },
|
|
{ "ULPTX_CPL_PACK_SIZE", 0x5a8, 0 },
|
|
{ "value", 24, 8 },
|
|
{ "Ch1Size2", 24, 8 },
|
|
{ "Ch1Size1", 16, 8 },
|
|
{ "Ch0Size2", 8, 8 },
|
|
{ "Ch0Size1", 0, 8 },
|
|
{ "ULPTX_DMA_WEIGHT", 0x5ac, 0 },
|
|
{ "D1_WEIGHT", 16, 16 },
|
|
{ "D0_WEIGHT", 0, 16 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_pm1_rx_regs[] = {
|
|
{ "PM1_RX_CFG", 0x5c0, 0 },
|
|
{ "PM1_RX_MODE", 0x5c4, 0 },
|
|
{ "stat_channel", 1, 1 },
|
|
{ "priority_ch", 0, 1 },
|
|
{ "PM1_RX_STAT_CONFIG", 0x5c8, 0 },
|
|
{ "PM1_RX_STAT_COUNT", 0x5cc, 0 },
|
|
{ "PM1_RX_STAT_MSB", 0x5d0, 0 },
|
|
{ "PM1_RX_STAT_LSB", 0x5d4, 0 },
|
|
{ "PM1_RX_INT_ENABLE", 0x5d8, 0 },
|
|
{ "zero_e_cmd_error", 18, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 16, 1 },
|
|
{ "iespi0_Rx_framing_error", 15, 1 },
|
|
{ "iespi1_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "ocspi0_Rx_framing_error", 11, 1 },
|
|
{ "ocspi1_Rx_framing_error", 10, 1 },
|
|
{ "ocspi0_Tx_framing_error", 9, 1 },
|
|
{ "ocspi1_Tx_framing_error", 8, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "iespi_par_error", 3, 3 },
|
|
{ "ocspi_par_error", 0, 3 },
|
|
{ "PM1_RX_INT_CAUSE", 0x5dc, 0 },
|
|
{ "zero_e_cmd_error", 18, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 16, 1 },
|
|
{ "iespi0_Rx_framing_error", 15, 1 },
|
|
{ "iespi1_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "ocspi0_Rx_framing_error", 11, 1 },
|
|
{ "ocspi1_Rx_framing_error", 10, 1 },
|
|
{ "ocspi0_Tx_framing_error", 9, 1 },
|
|
{ "ocspi1_Tx_framing_error", 8, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "iespi_par_error", 3, 3 },
|
|
{ "ocspi_par_error", 0, 3 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_pm1_tx_regs[] = {
|
|
{ "PM1_TX_CFG", 0x5e0, 0 },
|
|
{ "PM1_TX_MODE", 0x5e4, 0 },
|
|
{ "stat_channel", 1, 1 },
|
|
{ "priority_ch", 0, 1 },
|
|
{ "PM1_TX_STAT_CONFIG", 0x5e8, 0 },
|
|
{ "PM1_TX_STAT_COUNT", 0x5ec, 0 },
|
|
{ "PM1_TX_STAT_MSB", 0x5f0, 0 },
|
|
{ "PM1_TX_STAT_LSB", 0x5f4, 0 },
|
|
{ "PM1_TX_INT_ENABLE", 0x5f8, 0 },
|
|
{ "zero_c_cmd_error", 18, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 17, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 16, 1 },
|
|
{ "icspi0_Rx_framing_error", 15, 1 },
|
|
{ "icspi1_Rx_framing_error", 14, 1 },
|
|
{ "icspi0_Tx_framing_error", 13, 1 },
|
|
{ "icspi1_Tx_framing_error", 12, 1 },
|
|
{ "oespi0_Rx_framing_error", 11, 1 },
|
|
{ "oespi1_Rx_framing_error", 10, 1 },
|
|
{ "oespi0_Tx_framing_error", 9, 1 },
|
|
{ "oespi1_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "icspi_par_error", 3, 3 },
|
|
{ "oespi_par_error", 0, 3 },
|
|
{ "PM1_TX_INT_CAUSE", 0x5fc, 0 },
|
|
{ "zero_c_cmd_error", 18, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 17, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 16, 1 },
|
|
{ "icspi0_Rx_framing_error", 15, 1 },
|
|
{ "icspi1_Rx_framing_error", 14, 1 },
|
|
{ "icspi0_Tx_framing_error", 13, 1 },
|
|
{ "icspi1_Tx_framing_error", 12, 1 },
|
|
{ "oespi0_Rx_framing_error", 11, 1 },
|
|
{ "oespi1_Rx_framing_error", 10, 1 },
|
|
{ "oespi0_Tx_framing_error", 9, 1 },
|
|
{ "oespi1_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "icspi_par_error", 3, 3 },
|
|
{ "oespi_par_error", 0, 3 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mps0_regs[] = {
|
|
{ "MPS_CFG", 0x600, 0 },
|
|
{ "EnForcePkt", 11, 1 },
|
|
{ "SGETPQid", 8, 3 },
|
|
{ "TPRxPortSize", 7, 1 },
|
|
{ "TPTxPort1Size", 6, 1 },
|
|
{ "TPTxPort0Size", 5, 1 },
|
|
{ "TPRxPortEn", 4, 1 },
|
|
{ "TPTxPort1En", 3, 1 },
|
|
{ "TPTxPort0En", 2, 1 },
|
|
{ "Port1Active", 1, 1 },
|
|
{ "Port0Active", 0, 1 },
|
|
{ "MPS_DRR_CFG1", 0x604, 0 },
|
|
{ "RldWtTPD1", 11, 11 },
|
|
{ "RldWtTPD0", 0, 11 },
|
|
{ "MPS_DRR_CFG2", 0x608, 0 },
|
|
{ "RldWtTotal", 0, 12 },
|
|
{ "MPS_MCA_STATUS", 0x60c, 0 },
|
|
{ "MCAPktCnt", 12, 20 },
|
|
{ "MCADepth", 0, 12 },
|
|
{ "MPS_TX0_TP_CNT", 0x610, 0 },
|
|
{ "TX0TPDisCnt", 24, 8 },
|
|
{ "TX0TPCnt", 0, 24 },
|
|
{ "MPS_TX1_TP_CNT", 0x614, 0 },
|
|
{ "TX1TPDisCnt", 24, 8 },
|
|
{ "TX1TPCnt", 0, 24 },
|
|
{ "MPS_RX_TP_CNT", 0x618, 0 },
|
|
{ "RXTPDisCnt", 24, 8 },
|
|
{ "RXTPCnt", 0, 24 },
|
|
{ "MPS_INT_ENABLE", 0x61c, 0 },
|
|
{ "MCAParErrEnb", 6, 3 },
|
|
{ "RXTpParErrEnb", 4, 2 },
|
|
{ "TX1TpParErrEnb", 2, 2 },
|
|
{ "TX0TpParErrEnb", 0, 2 },
|
|
{ "MPS_INT_CAUSE", 0x620, 0 },
|
|
{ "MCAParErr", 6, 3 },
|
|
{ "RXTpParErr", 4, 2 },
|
|
{ "TX1TpParErr", 2, 2 },
|
|
{ "TX0TpParErr", 0, 2 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_cpl_switch_regs[] = {
|
|
{ "CPL_SWITCH_CNTRL", 0x640, 0 },
|
|
{ "cpl_pkt_tid", 8, 24 },
|
|
{ "cim_to_up_full_size", 4, 1 },
|
|
{ "cpu_no_3F_CIM_enable", 3, 1 },
|
|
{ "switch_table_enable", 2, 1 },
|
|
{ "sge_enable", 1, 1 },
|
|
{ "cim_enable", 0, 1 },
|
|
{ "CPL_SWITCH_TBL_IDX", 0x644, 0 },
|
|
{ "switch_tbl_idx", 0, 4 },
|
|
{ "CPL_SWITCH_TBL_DATA", 0x648, 0 },
|
|
{ "CPL_SWITCH_ZERO_ERROR", 0x64c, 0 },
|
|
{ "zero_cmd", 0, 8 },
|
|
{ "CPL_INTR_ENABLE", 0x650, 0 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_INTR_CAUSE", 0x654, 0 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_MAP_TBL_IDX", 0x658, 0 },
|
|
{ "cpl_map_tbl_idx", 0, 8 },
|
|
{ "CPL_MAP_TBL_DATA", 0x65c, 0 },
|
|
{ "cpl_map_tbl_data", 0, 8 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_smb0_regs[] = {
|
|
{ "SMB_GLOBAL_TIME_CFG", 0x660, 0 },
|
|
{ "LADbgWrPtr", 24, 8 },
|
|
{ "LADbgRdPtr", 16, 8 },
|
|
{ "LADbgEn", 13, 1 },
|
|
{ "MacroCntCfg", 8, 5 },
|
|
{ "MicroCntCfg", 0, 8 },
|
|
{ "SMB_MST_TIMEOUT_CFG", 0x664, 0 },
|
|
{ "DebugSelH", 28, 4 },
|
|
{ "DebugSelL", 24, 4 },
|
|
{ "MstTimeOutCfg", 0, 24 },
|
|
{ "SMB_MST_CTL_CFG", 0x668, 0 },
|
|
{ "MstFifoDbg", 31, 1 },
|
|
{ "MstFifoDbgClr", 30, 1 },
|
|
{ "MstRxByteCfg", 12, 6 },
|
|
{ "MstTxByteCfg", 6, 6 },
|
|
{ "MstReset", 1, 1 },
|
|
{ "MstCtlEn", 0, 1 },
|
|
{ "SMB_MST_CTL_STS", 0x66c, 0 },
|
|
{ "MstRxByteCnt", 12, 6 },
|
|
{ "MstTxByteCnt", 6, 6 },
|
|
{ "MstBusySts", 0, 1 },
|
|
{ "SMB_MST_TX_FIFO_RDWR", 0x670, 0 },
|
|
{ "SMB_MST_RX_FIFO_RDWR", 0x674, 0 },
|
|
{ "SMB_SLV_TIMEOUT_CFG", 0x678, 0 },
|
|
{ "SlvTimeOutCfg", 0, 24 },
|
|
{ "SMB_SLV_CTL_CFG", 0x67c, 0 },
|
|
{ "SlvFifoDbg", 31, 1 },
|
|
{ "SlvFifoDbgClr", 30, 1 },
|
|
{ "SlvAddrCfg", 4, 7 },
|
|
{ "SlvAlrtSet", 2, 1 },
|
|
{ "SlvReset", 1, 1 },
|
|
{ "SlvCtlEn", 0, 1 },
|
|
{ "SMB_SLV_CTL_STS", 0x680, 0 },
|
|
{ "SlvFifoTxCnt", 12, 6 },
|
|
{ "SlvFifoCnt", 6, 6 },
|
|
{ "SlvAlrtSts", 2, 1 },
|
|
{ "SlvBusySts", 0, 1 },
|
|
{ "SMB_SLV_FIFO_RDWR", 0x684, 0 },
|
|
{ "SMB_SLV_CMD_FIFO_RDWR", 0x688, 0 },
|
|
{ "SMB_INT_ENABLE", 0x68c, 0 },
|
|
{ "SlvTimeOutIntEn", 7, 1 },
|
|
{ "SlvErrIntEn", 6, 1 },
|
|
{ "SlvDoneIntEn", 5, 1 },
|
|
{ "SlvRxRdyIntEn", 4, 1 },
|
|
{ "MstTimeOutIntEn", 3, 1 },
|
|
{ "MstNAckIntEn", 2, 1 },
|
|
{ "MstLostArbIntEn", 1, 1 },
|
|
{ "MstDoneIntEn", 0, 1 },
|
|
{ "SMB_INT_CAUSE", 0x690, 0 },
|
|
{ "SlvTimeOutInt", 7, 1 },
|
|
{ "SlvErrInt", 6, 1 },
|
|
{ "SlvDoneInt", 5, 1 },
|
|
{ "SlvRxRdyInt", 4, 1 },
|
|
{ "MstTimeOutInt", 3, 1 },
|
|
{ "MstNAckInt", 2, 1 },
|
|
{ "MstLostArbInt", 1, 1 },
|
|
{ "MstDoneInt", 0, 1 },
|
|
{ "SMB_DEBUG_DATA", 0x694, 0 },
|
|
{ "DebugDataH", 16, 16 },
|
|
{ "DebugDataL", 0, 16 },
|
|
{ "SMB_DEBUG_LA", 0x69c, 0 },
|
|
{ "DebugLAReqAddr", 0, 10 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_i2cm0_regs[] = {
|
|
{ "I2C_CFG", 0x6a0, 0 },
|
|
{ "ClkDiv", 0, 12 },
|
|
{ "I2C_DATA", 0x6a4, 0 },
|
|
{ "Data", 0, 8 },
|
|
{ "I2C_OP", 0x6a8, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Ack", 30, 1 },
|
|
{ "Cont", 1, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mi1_regs[] = {
|
|
{ "MI1_CFG", 0x6b0, 0 },
|
|
{ "ClkDiv", 5, 8 },
|
|
{ "St", 3, 2 },
|
|
{ "PreEn", 2, 1 },
|
|
{ "MDIInv", 1, 1 },
|
|
{ "MDIEn", 0, 1 },
|
|
{ "MI1_ADDR", 0x6b4, 0 },
|
|
{ "PhyAddr", 5, 5 },
|
|
{ "RegAddr", 0, 5 },
|
|
{ "MI1_DATA", 0x6b8, 0 },
|
|
{ "Data", 0, 16 },
|
|
{ "MI1_OP", 0x6bc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Inc", 2, 1 },
|
|
{ "Op", 0, 2 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_jm1_regs[] = {
|
|
{ "JM_CFG", 0x6c0, 0 },
|
|
{ "ClkDiv", 2, 8 },
|
|
{ "TRst", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "JM_MODE", 0x6c4, 0 },
|
|
{ "JM_DATA", 0x6c8, 0 },
|
|
{ "JM_OP", 0x6cc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Cnt", 0, 5 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_sf1_regs[] = {
|
|
{ "SF_DATA", 0x6d8, 0 },
|
|
{ "SF_OP", 0x6dc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Cont", 3, 1 },
|
|
{ "ByteCnt", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_pl3_regs[] = {
|
|
{ "PL_INT_ENABLE0", 0x6e0, 0 },
|
|
{ "SW", 25, 1 },
|
|
{ "EXT", 24, 1 },
|
|
{ "T3DBG", 23, 1 },
|
|
{ "XGMAC0_1", 20, 1 },
|
|
{ "XGMAC0_0", 19, 1 },
|
|
{ "MC5A", 18, 1 },
|
|
{ "SF1", 17, 1 },
|
|
{ "SMB0", 15, 1 },
|
|
{ "I2CM0", 14, 1 },
|
|
{ "MI1", 13, 1 },
|
|
{ "CPL_SWITCH", 12, 1 },
|
|
{ "MPS0", 11, 1 },
|
|
{ "PM1_TX", 10, 1 },
|
|
{ "PM1_RX", 9, 1 },
|
|
{ "ULP2_TX", 8, 1 },
|
|
{ "ULP2_RX", 7, 1 },
|
|
{ "TP1", 6, 1 },
|
|
{ "CIM", 5, 1 },
|
|
{ "MC7_CM", 4, 1 },
|
|
{ "MC7_PMTX", 3, 1 },
|
|
{ "MC7_PMRX", 2, 1 },
|
|
{ "PCIM0", 1, 1 },
|
|
{ "SGE3", 0, 1 },
|
|
{ "PL_INT_CAUSE0", 0x6e4, 0 },
|
|
{ "SW", 25, 1 },
|
|
{ "EXT", 24, 1 },
|
|
{ "T3DBG", 23, 1 },
|
|
{ "XGMAC0_1", 20, 1 },
|
|
{ "XGMAC0_0", 19, 1 },
|
|
{ "MC5A", 18, 1 },
|
|
{ "SF1", 17, 1 },
|
|
{ "SMB0", 15, 1 },
|
|
{ "I2CM0", 14, 1 },
|
|
{ "MI1", 13, 1 },
|
|
{ "CPL_SWITCH", 12, 1 },
|
|
{ "MPS0", 11, 1 },
|
|
{ "PM1_TX", 10, 1 },
|
|
{ "PM1_RX", 9, 1 },
|
|
{ "ULP2_TX", 8, 1 },
|
|
{ "ULP2_RX", 7, 1 },
|
|
{ "TP1", 6, 1 },
|
|
{ "CIM", 5, 1 },
|
|
{ "MC7_CM", 4, 1 },
|
|
{ "MC7_PMTX", 3, 1 },
|
|
{ "MC7_PMRX", 2, 1 },
|
|
{ "PCIM0", 1, 1 },
|
|
{ "SGE3", 0, 1 },
|
|
{ "PL_INT_ENABLE1", 0x6e8, 0 },
|
|
{ "SW", 25, 1 },
|
|
{ "EXT", 24, 1 },
|
|
{ "T3DBG", 23, 1 },
|
|
{ "XGMAC0_1", 20, 1 },
|
|
{ "XGMAC0_0", 19, 1 },
|
|
{ "MC5A", 18, 1 },
|
|
{ "SF1", 17, 1 },
|
|
{ "SMB0", 15, 1 },
|
|
{ "I2CM0", 14, 1 },
|
|
{ "MI1", 13, 1 },
|
|
{ "CPL_SWITCH", 12, 1 },
|
|
{ "MPS0", 11, 1 },
|
|
{ "PM1_TX", 10, 1 },
|
|
{ "PM1_RX", 9, 1 },
|
|
{ "ULP2_TX", 8, 1 },
|
|
{ "ULP2_RX", 7, 1 },
|
|
{ "TP1", 6, 1 },
|
|
{ "CIM", 5, 1 },
|
|
{ "MC7_CM", 4, 1 },
|
|
{ "MC7_PMTX", 3, 1 },
|
|
{ "MC7_PMRX", 2, 1 },
|
|
{ "PCIM0", 1, 1 },
|
|
{ "SGE3", 0, 1 },
|
|
{ "PL_INT_CAUSE1", 0x6ec, 0 },
|
|
{ "SW", 25, 1 },
|
|
{ "EXT", 24, 1 },
|
|
{ "T3DBG", 23, 1 },
|
|
{ "XGMAC0_1", 20, 1 },
|
|
{ "XGMAC0_0", 19, 1 },
|
|
{ "MC5A", 18, 1 },
|
|
{ "SF1", 17, 1 },
|
|
{ "SMB0", 15, 1 },
|
|
{ "I2CM0", 14, 1 },
|
|
{ "MI1", 13, 1 },
|
|
{ "CPL_SWITCH", 12, 1 },
|
|
{ "MPS0", 11, 1 },
|
|
{ "PM1_TX", 10, 1 },
|
|
{ "PM1_RX", 9, 1 },
|
|
{ "ULP2_TX", 8, 1 },
|
|
{ "ULP2_RX", 7, 1 },
|
|
{ "TP1", 6, 1 },
|
|
{ "CIM", 5, 1 },
|
|
{ "MC7_CM", 4, 1 },
|
|
{ "MC7_PMTX", 3, 1 },
|
|
{ "MC7_PMRX", 2, 1 },
|
|
{ "PCIM0", 1, 1 },
|
|
{ "SGE3", 0, 1 },
|
|
{ "PL_RST", 0x6f0, 0 },
|
|
{ "FatalPerrEn", 4, 1 },
|
|
{ "SWInt1", 3, 1 },
|
|
{ "SWInt0", 2, 1 },
|
|
{ "CRstWrm", 1, 1 },
|
|
{ "CRstWrmMode", 0, 1 },
|
|
{ "PL_REV", 0x6f4, 0 },
|
|
{ "Rev", 0, 4 },
|
|
{ "PL_CLI", 0x6f8, 0 },
|
|
{ "PL_LCK", 0x6fc, 0 },
|
|
{ "Lck", 0, 2 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_mc5a_regs[] = {
|
|
{ "MC5_BUF_CONFIG", 0x700, 0 },
|
|
{ "term300_240", 31, 1 },
|
|
{ "term150", 30, 1 },
|
|
{ "term60", 29, 1 },
|
|
{ "gddriii", 28, 1 },
|
|
{ "gddrii", 27, 1 },
|
|
{ "gddri", 26, 1 },
|
|
{ "read", 25, 1 },
|
|
{ "imp_set_update", 24, 1 },
|
|
{ "cal_update", 23, 1 },
|
|
{ "cal_busy", 22, 1 },
|
|
{ "cal_error", 21, 1 },
|
|
{ "sgl_cal_en", 20, 1 },
|
|
{ "imp_upd_mode", 19, 1 },
|
|
{ "imp_sel", 18, 1 },
|
|
{ "man_pu", 15, 3 },
|
|
{ "man_pd", 12, 3 },
|
|
{ "cal_pu", 9, 3 },
|
|
{ "cal_pd", 6, 3 },
|
|
{ "set_pu", 3, 3 },
|
|
{ "set_pd", 0, 3 },
|
|
{ "MC5_DB_CONFIG", 0x704, 0 },
|
|
{ "TMCfgWrLock", 31, 1 },
|
|
{ "TMTypeHi", 30, 1 },
|
|
{ "TMPartSize", 28, 2 },
|
|
{ "TMType", 26, 2 },
|
|
{ "TMPartCount", 24, 2 },
|
|
{ "nLIP", 18, 6 },
|
|
{ "COMPEN", 17, 1 },
|
|
{ "BUILD", 16, 1 },
|
|
{ "FilterEn", 11, 1 },
|
|
{ "CLIPUpdate", 10, 1 },
|
|
{ "TM_IO_PDOWN", 9, 1 },
|
|
{ "SYNMode", 7, 2 },
|
|
{ "PRTYEN", 6, 1 },
|
|
{ "MBUSEN", 5, 1 },
|
|
{ "DBGIEN", 4, 1 },
|
|
{ "TcmCfgOvr", 3, 1 },
|
|
{ "TMRDY", 2, 1 },
|
|
{ "TMRST", 1, 1 },
|
|
{ "TMMode", 0, 1 },
|
|
{ "MC5_MISC", 0x708, 0 },
|
|
{ "LIP_Cmp_Unavailable", 0, 4 },
|
|
{ "MC5_DB_ROUTING_TABLE_INDEX", 0x70c, 0 },
|
|
{ "RTINDX", 0, 22 },
|
|
{ "MC5_DB_FILTER_TABLE", 0x710, 0 },
|
|
{ "SRINDX", 0, 22 },
|
|
{ "MC5_DB_SERVER_INDEX", 0x714, 0 },
|
|
{ "SRINDX", 0, 22 },
|
|
{ "MC5_DB_LIP_RAM_ADDR", 0x718, 0 },
|
|
{ "RAMWR", 8, 1 },
|
|
{ "RAMADDR", 0, 6 },
|
|
{ "MC5_DB_LIP_RAM_DATA", 0x71c, 0 },
|
|
{ "MC5_DB_RSP_LATENCY", 0x720, 0 },
|
|
{ "RDLAT", 16, 5 },
|
|
{ "LRNLAT", 8, 5 },
|
|
{ "SRCHLAT", 0, 5 },
|
|
{ "MC5_DB_PARITY_LATENCY", 0x724, 0 },
|
|
{ "PARLAT", 0, 4 },
|
|
{ "MC5_DB_WR_LRN_VERIFY", 0x728, 0 },
|
|
{ "VWVEREN", 2, 1 },
|
|
{ "LRNVEREN", 1, 1 },
|
|
{ "POVEREN", 0, 1 },
|
|
{ "MC5_DB_PART_ID_INDEX", 0x72c, 0 },
|
|
{ "IDINDEX", 0, 4 },
|
|
{ "MC5_DB_RESET_MAX", 0x730, 0 },
|
|
{ "RSTMAX", 0, 4 },
|
|
{ "MC5_DB_ACT_CNT", 0x734, 0 },
|
|
{ "ACTCNT", 0, 20 },
|
|
{ "MC5_DB_CLIP_MAP", 0x738, 0 },
|
|
{ "CLIPMapOp", 31, 1 },
|
|
{ "CLIPMapVal", 16, 6 },
|
|
{ "CLIPMapAddr", 0, 6 },
|
|
{ "MC5_DB_SIZE", 0x73c, 0 },
|
|
{ "MC5_DB_INT_ENABLE", 0x740, 0 },
|
|
{ "MsgSel", 28, 4 },
|
|
{ "DelActEmpty", 18, 1 },
|
|
{ "DispQParErr", 17, 1 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ActiveOutHit", 0, 1 },
|
|
{ "MC5_DB_INT_CAUSE", 0x744, 0 },
|
|
{ "DelActEmpty", 18, 1 },
|
|
{ "DispQParErr", 17, 1 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ActiveOutHit", 0, 1 },
|
|
{ "MC5_DB_INT_TID", 0x748, 0 },
|
|
{ "INTTID", 0, 20 },
|
|
{ "MC5_DB_INT_PTID", 0x74c, 0 },
|
|
{ "INTPTID", 0, 20 },
|
|
{ "MC5_DB_DBGI_CONFIG", 0x774, 0 },
|
|
{ "WRReqSize", 22, 10 },
|
|
{ "SADRSel", 4, 1 },
|
|
{ "CMDMode", 0, 3 },
|
|
{ "MC5_DB_DBGI_REQ_CMD", 0x778, 0 },
|
|
{ "MBusCmd", 0, 4 },
|
|
{ "IDTCmdHi", 11, 3 },
|
|
{ "IDTCmdLo", 0, 4 },
|
|
{ "IDTCmd", 0, 20 },
|
|
{ "LCMDB", 16, 11 },
|
|
{ "LCMDA", 0, 11 },
|
|
{ "MC5_DB_DBGI_REQ_ADDR0", 0x77c, 0 },
|
|
{ "MC5_DB_DBGI_REQ_ADDR1", 0x780, 0 },
|
|
{ "MC5_DB_DBGI_REQ_ADDR2", 0x784, 0 },
|
|
{ "DBGIReqAdrHi", 0, 8 },
|
|
{ "MC5_DB_DBGI_REQ_DATA0", 0x788, 0 },
|
|
{ "MC5_DB_DBGI_REQ_DATA1", 0x78c, 0 },
|
|
{ "MC5_DB_DBGI_REQ_DATA2", 0x790, 0 },
|
|
{ "MC5_DB_DBGI_REQ_DATA3", 0x794, 0 },
|
|
{ "MC5_DB_DBGI_REQ_DATA4", 0x798, 0 },
|
|
{ "DBGIReqData4", 0, 16 },
|
|
{ "MC5_DB_DBGI_REQ_MASK0", 0x79c, 0 },
|
|
{ "MC5_DB_DBGI_REQ_MASK1", 0x7a0, 0 },
|
|
{ "MC5_DB_DBGI_REQ_MASK2", 0x7a4, 0 },
|
|
{ "MC5_DB_DBGI_REQ_MASK3", 0x7a8, 0 },
|
|
{ "MC5_DB_DBGI_REQ_MASK4", 0x7ac, 0 },
|
|
{ "DBGIReqMsk4", 0, 16 },
|
|
{ "MC5_DB_DBGI_RSP_STATUS", 0x7b0, 0 },
|
|
{ "DBGIRspMsg", 8, 4 },
|
|
{ "DBGIRspMsgVld", 2, 1 },
|
|
{ "DBGIRspHit", 1, 1 },
|
|
{ "DBGIRspValid", 0, 1 },
|
|
{ "MC5_DB_DBGI_RSP_DATA0", 0x7b4, 0 },
|
|
{ "MC5_DB_DBGI_RSP_DATA1", 0x7b8, 0 },
|
|
{ "MC5_DB_DBGI_RSP_DATA2", 0x7bc, 0 },
|
|
{ "MC5_DB_DBGI_RSP_DATA3", 0x7c0, 0 },
|
|
{ "MC5_DB_DBGI_RSP_DATA4", 0x7c4, 0 },
|
|
{ "DBGIRspData3", 0, 16 },
|
|
{ "MC5_DB_DBGI_RSP_LAST_CMD", 0x7c8, 0 },
|
|
{ "LastCmdB", 16, 11 },
|
|
{ "LastCmdA", 0, 11 },
|
|
{ "MC5_DB_POPEN_DATA_WR_CMD", 0x7cc, 0 },
|
|
{ "PO_DWR", 0, 20 },
|
|
{ "MC5_DB_POPEN_MASK_WR_CMD", 0x7d0, 0 },
|
|
{ "PO_MWR", 0, 20 },
|
|
{ "MC5_DB_AOPEN_SRCH_CMD", 0x7d4, 0 },
|
|
{ "AO_SRCH", 0, 20 },
|
|
{ "MC5_DB_AOPEN_LRN_CMD", 0x7d8, 0 },
|
|
{ "AO_LRN", 0, 20 },
|
|
{ "MC5_DB_SYN_SRCH_CMD", 0x7dc, 0 },
|
|
{ "SYN_SRCH", 0, 20 },
|
|
{ "MC5_DB_SYN_LRN_CMD", 0x7e0, 0 },
|
|
{ "SYN_LRN", 0, 20 },
|
|
{ "MC5_DB_ACK_SRCH_CMD", 0x7e4, 0 },
|
|
{ "ACK_SRCH", 0, 20 },
|
|
{ "MC5_DB_ACK_LRN_CMD", 0x7e8, 0 },
|
|
{ "ACK_LRN", 0, 20 },
|
|
{ "MC5_DB_ILOOKUP_CMD", 0x7ec, 0 },
|
|
{ "I_SRCH", 0, 20 },
|
|
{ "MC5_DB_ELOOKUP_CMD", 0x7f0, 0 },
|
|
{ "E_SRCH", 0, 20 },
|
|
{ "MC5_DB_DATA_WRITE_CMD", 0x7f4, 0 },
|
|
{ "Write", 0, 20 },
|
|
{ "MC5_DB_DATA_READ_CMD", 0x7f8, 0 },
|
|
{ "ReadCmd", 0, 20 },
|
|
{ "MC5_DB_MASK_WRITE_CMD", 0x7fc, 0 },
|
|
{ "MaskWr", 0, 16 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_xgmac0_0_regs[] = {
|
|
{ "XGM_TX_CTRL", 0x800, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGM_TX_CFG", 0x804, 0 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGM_TX_PAUSE_QUANTA", 0x808, 0 },
|
|
{ "TxPauseQuanta", 0, 16 },
|
|
{ "XGM_RX_CTRL", 0x80c, 0 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "XGM_RX_CFG", 0x810, 0 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGM_RX_HASH_LOW", 0x814, 0 },
|
|
{ "XGM_RX_HASH_HIGH", 0x818, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_1", 0x81c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_1", 0x820, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_2", 0x824, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_2", 0x828, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_3", 0x82c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_3", 0x830, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_4", 0x834, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_4", 0x838, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_5", 0x83c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_5", 0x840, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_6", 0x844, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_6", 0x848, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_7", 0x84c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_7", 0x850, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_8", 0x854, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_8", 0x858, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_1", 0x85c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_2", 0x860, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_3", 0x864, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_4", 0x868, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_INT_STATUS", 0x86c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_MASK", 0x870, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_ENABLE", 0x874, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_DISABLE", 0x878, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_TX_PAUSE_TIMER", 0x87c, 0 },
|
|
{ "CurPauseTimer", 0, 16 },
|
|
{ "XGM_STAT_CTRL", 0x880, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGM_RXFIFO_CFG", 0x884, 0 },
|
|
{ "RxFIFO_empty", 31, 1 },
|
|
{ "RxFIFO_full", 30, 1 },
|
|
{ "RxFIFOPauseHWM", 17, 12 },
|
|
{ "RxFIFOPauseLWM", 5, 12 },
|
|
{ "ForcedPause", 4, 1 },
|
|
{ "ExternLoopback", 3, 1 },
|
|
{ "RxByteSwap", 2, 1 },
|
|
{ "RxStrFrwrd", 1, 1 },
|
|
{ "DisErrFrames", 0, 1 },
|
|
{ "XGM_TXFIFO_CFG", 0x888, 0 },
|
|
{ "TxFIFO_empty", 31, 1 },
|
|
{ "TxFIFO_full", 30, 1 },
|
|
{ "UnderunFix", 22, 1 },
|
|
{ "EnDropPkt", 21, 1 },
|
|
{ "TxIPG", 13, 8 },
|
|
{ "TxFIFOThresh", 4, 9 },
|
|
{ "InternLoopback", 3, 1 },
|
|
{ "TxByteSwap", 2, 1 },
|
|
{ "DisCRC", 1, 1 },
|
|
{ "DisPreAmble", 0, 1 },
|
|
{ "XGM_SLOW_TIMER", 0x88c, 0 },
|
|
{ "PauseSlowTimerEn", 31, 1 },
|
|
{ "PauseSlowTimer", 0, 20 },
|
|
{ "XGM_PAUSE_TIMER", 0x890, 0 },
|
|
{ "PauseTimer", 0, 20 },
|
|
{ "XGM_XAUI_PCS_TEST", 0x894, 0 },
|
|
{ "TestPattern", 1, 2 },
|
|
{ "EnTest", 0, 1 },
|
|
{ "XGM_RGMII_CTRL", 0x898, 0 },
|
|
{ "PhAlignFIFOThresh", 1, 2 },
|
|
{ "TxClk90Shift", 0, 1 },
|
|
{ "XGM_RGMII_IMP", 0x89c, 0 },
|
|
{ "CalReset", 8, 1 },
|
|
{ "CalUpdate", 7, 1 },
|
|
{ "ImpSetUpdate", 6, 1 },
|
|
{ "RGMIIImpPD", 3, 3 },
|
|
{ "RGMIIImpPU", 0, 3 },
|
|
{ "XGM_RX_MAX_PKT_SIZE", 0x8a8, 0 },
|
|
{ "RxMaxFramerSize", 17, 14 },
|
|
{ "RxEnErrorGather", 16, 1 },
|
|
{ "RxEnSingleFlit", 15, 1 },
|
|
{ "RxEnFramer", 14, 1 },
|
|
{ "RxMaxPktSize", 0, 14 },
|
|
{ "XGM_RESET_CTRL", 0x8ac, 0 },
|
|
{ "XGMAC_STOP_EN", 4, 1 },
|
|
{ "XG2G_Reset_", 3, 1 },
|
|
{ "RGMII_Reset_", 2, 1 },
|
|
{ "PCS_Reset_", 1, 1 },
|
|
{ "MAC_Reset_", 0, 1 },
|
|
{ "XGM_XAUI1G_CTRL", 0x8b0, 0 },
|
|
{ "XAUI1GLinkId", 0, 2 },
|
|
{ "XGM_SERDES_LANE_CTRL", 0x8b4, 0 },
|
|
{ "LaneReversal", 8, 1 },
|
|
{ "TxPolarity", 4, 4 },
|
|
{ "RxPolarity", 0, 4 },
|
|
{ "XGM_PORT_CFG", 0x8b8, 0 },
|
|
{ "SafeSpeedChange", 4, 1 },
|
|
{ "ClkDivReset_", 3, 1 },
|
|
{ "PortSpeed", 1, 2 },
|
|
{ "EnRGMII", 0, 1 },
|
|
{ "XGM_EPIO_DATA0", 0x8c0, 0 },
|
|
{ "XGM_EPIO_DATA1", 0x8c4, 0 },
|
|
{ "XGM_EPIO_DATA2", 0x8c8, 0 },
|
|
{ "XGM_EPIO_DATA3", 0x8cc, 0 },
|
|
{ "XGM_EPIO_OP", 0x8d0, 0 },
|
|
{ "PIO_Ready", 31, 1 },
|
|
{ "PIO_WrRd", 24, 1 },
|
|
{ "PIO_Address", 0, 8 },
|
|
{ "XGM_INT_ENABLE", 0x8d4, 0 },
|
|
{ "XAUIPCSDECErr", 24, 1 },
|
|
{ "RGMIIRxFIFOOverflow", 23, 1 },
|
|
{ "RGMIIRxFIFOUnderflow", 22, 1 },
|
|
{ "RxPktSizeError", 21, 1 },
|
|
{ "WOLPatDetected", 20, 1 },
|
|
{ "TXFIFO_prty_err", 17, 3 },
|
|
{ "RXFIFO_prty_err", 14, 3 },
|
|
{ "TXFIFO_underrun", 13, 1 },
|
|
{ "RXFIFO_overflow", 12, 1 },
|
|
{ "SERDESBISTErr", 8, 4 },
|
|
{ "SERDESLowSigChange", 4, 4 },
|
|
{ "XAUIPCSCTCErr", 3, 1 },
|
|
{ "XAUIPCSAlignChange", 2, 1 },
|
|
{ "RGMIILinkStsChange", 1, 1 },
|
|
{ "xgm_int", 0, 1 },
|
|
{ "XGM_INT_CAUSE", 0x8d8, 0 },
|
|
{ "XAUIPCSDECErr", 24, 1 },
|
|
{ "RGMIIRxFIFOOverflow", 23, 1 },
|
|
{ "RGMIIRxFIFOUnderflow", 22, 1 },
|
|
{ "RxPktSizeError", 21, 1 },
|
|
{ "WOLPatDetected", 20, 1 },
|
|
{ "TXFIFO_prty_err", 17, 3 },
|
|
{ "RXFIFO_prty_err", 14, 3 },
|
|
{ "TXFIFO_underrun", 13, 1 },
|
|
{ "RXFIFO_overflow", 12, 1 },
|
|
{ "SERDESBISTErr", 8, 4 },
|
|
{ "SERDESLowSigChange", 4, 4 },
|
|
{ "XAUIPCSCTCErr", 3, 1 },
|
|
{ "XAUIPCSAlignChange", 2, 1 },
|
|
{ "RGMIILinkStsChange", 1, 1 },
|
|
{ "xgm_int", 0, 1 },
|
|
{ "XGM_XAUI_ACT_CTRL", 0x8dc, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "XGM_SERDES_CTRL0", 0x8e0, 0 },
|
|
{ "IntSerLPBK3", 27, 1 },
|
|
{ "IntSerLPBK2", 26, 1 },
|
|
{ "IntSerLPBK1", 25, 1 },
|
|
{ "IntSerLPBK0", 24, 1 },
|
|
{ "Reset3", 23, 1 },
|
|
{ "Reset2", 22, 1 },
|
|
{ "Reset1", 21, 1 },
|
|
{ "Reset0", 20, 1 },
|
|
{ "Pwrdn3", 19, 1 },
|
|
{ "Pwrdn2", 18, 1 },
|
|
{ "Pwrdn1", 17, 1 },
|
|
{ "Pwrdn0", 16, 1 },
|
|
{ "ResetPLL23", 15, 1 },
|
|
{ "ResetPLL01", 14, 1 },
|
|
{ "PW23", 12, 2 },
|
|
{ "PW01", 10, 2 },
|
|
{ "Deq", 6, 4 },
|
|
{ "Dtx", 2, 4 },
|
|
{ "LoDrv", 1, 1 },
|
|
{ "HiDrv", 0, 1 },
|
|
{ "XGM_SERDES_CTRL1", 0x8e4, 0 },
|
|
{ "FmOffset3", 19, 5 },
|
|
{ "FmOffsetEn3", 18, 1 },
|
|
{ "FmOffset2", 13, 5 },
|
|
{ "FmOffsetEn2", 12, 1 },
|
|
{ "FmOffset1", 7, 5 },
|
|
{ "FmOffsetEn1", 6, 1 },
|
|
{ "FmOffset0", 1, 5 },
|
|
{ "FmOffsetEn0", 0, 1 },
|
|
{ "XGM_SERDES_CTRL2", 0x8e8, 0 },
|
|
{ "DnIn3", 11, 1 },
|
|
{ "UpIn3", 10, 1 },
|
|
{ "RxSlave3", 9, 1 },
|
|
{ "DnIn2", 8, 1 },
|
|
{ "UpIn2", 7, 1 },
|
|
{ "RxSlave2", 6, 1 },
|
|
{ "DnIn1", 5, 1 },
|
|
{ "UpIn1", 4, 1 },
|
|
{ "RxSlave1", 3, 1 },
|
|
{ "DnIn0", 2, 1 },
|
|
{ "UpIn0", 1, 1 },
|
|
{ "RxSlave0", 0, 1 },
|
|
{ "XGM_SERDES_CTRL3", 0x8ec, 0 },
|
|
{ "ExtBISTChkErrClr3", 31, 1 },
|
|
{ "ExtBISTChkEn3", 30, 1 },
|
|
{ "ExtBISTGenEn3", 29, 1 },
|
|
{ "ExtBISTPat3", 26, 3 },
|
|
{ "ExtParReset3", 25, 1 },
|
|
{ "ExtParLPBK3", 24, 1 },
|
|
{ "ExtBISTChkErrClr2", 23, 1 },
|
|
{ "ExtBISTChkEn2", 22, 1 },
|
|
{ "ExtBISTGenEn2", 21, 1 },
|
|
{ "ExtBISTPat2", 18, 3 },
|
|
{ "ExtParReset2", 17, 1 },
|
|
{ "ExtParLPBK2", 16, 1 },
|
|
{ "ExtBISTChkErrClr1", 15, 1 },
|
|
{ "ExtBISTChkEn1", 14, 1 },
|
|
{ "ExtBISTGenEn1", 13, 1 },
|
|
{ "ExtBISTPat1", 10, 3 },
|
|
{ "ExtParReset1", 9, 1 },
|
|
{ "ExtParLPBK1", 8, 1 },
|
|
{ "ExtBISTChkErrClr0", 7, 1 },
|
|
{ "ExtBISTChkEn0", 6, 1 },
|
|
{ "ExtBISTGenEn0", 5, 1 },
|
|
{ "ExtBISTPat0", 2, 3 },
|
|
{ "ExtParReset0", 1, 1 },
|
|
{ "ExtParLPBK0", 0, 1 },
|
|
{ "XGM_SERDES_STAT0", 0x8f0, 0 },
|
|
{ "ExtBISTChkErrCnt0", 4, 24 },
|
|
{ "ExtBISTChkFmd0", 3, 1 },
|
|
{ "LowSigForceEn0", 2, 1 },
|
|
{ "LowSigForceValue0", 1, 1 },
|
|
{ "LowSig0", 0, 1 },
|
|
{ "XGM_SERDES_STAT1", 0x8f4, 0 },
|
|
{ "ExtBISTChkErrCnt1", 4, 24 },
|
|
{ "ExtBISTChkFmd1", 3, 1 },
|
|
{ "LowSigForceEn1", 2, 1 },
|
|
{ "LowSigForceValue1", 1, 1 },
|
|
{ "LowSig1", 0, 1 },
|
|
{ "XGM_SERDES_STAT2", 0x8f8, 0 },
|
|
{ "ExtBISTChkErrCnt2", 4, 24 },
|
|
{ "ExtBISTChkFmd2", 3, 1 },
|
|
{ "LowSigForceEn2", 2, 1 },
|
|
{ "LowSigForceValue2", 1, 1 },
|
|
{ "LowSig2", 0, 1 },
|
|
{ "XGM_SERDES_STAT3", 0x8fc, 0 },
|
|
{ "ExtBISTChkErrCnt3", 4, 24 },
|
|
{ "ExtBISTChkFmd3", 3, 1 },
|
|
{ "LowSigForceEn3", 2, 1 },
|
|
{ "LowSigForceValue3", 1, 1 },
|
|
{ "LowSig3", 0, 1 },
|
|
{ "XGM_STAT_TX_BYTE_LOW", 0x900, 0 },
|
|
{ "XGM_STAT_TX_BYTE_HIGH", 0x904, 0 },
|
|
{ "TxBytes_high", 0, 13 },
|
|
{ "XGM_STAT_TX_FRAME_LOW", 0x908, 0 },
|
|
{ "XGM_STAT_TX_FRAME_HIGH", 0x90c, 0 },
|
|
{ "TxFrames_high", 0, 4 },
|
|
{ "XGM_STAT_TX_BCAST", 0x910, 0 },
|
|
{ "XGM_STAT_TX_MCAST", 0x914, 0 },
|
|
{ "XGM_STAT_TX_PAUSE", 0x918, 0 },
|
|
{ "XGM_STAT_TX_64B_FRAMES", 0x91c, 0 },
|
|
{ "XGM_STAT_TX_65_127B_FRAMES", 0x920, 0 },
|
|
{ "XGM_STAT_TX_128_255B_FRAMES", 0x924, 0 },
|
|
{ "XGM_STAT_TX_256_511B_FRAMES", 0x928, 0 },
|
|
{ "XGM_STAT_TX_512_1023B_FRAMES", 0x92c, 0 },
|
|
{ "XGM_STAT_TX_1024_1518B_FRAMES", 0x930, 0 },
|
|
{ "XGM_STAT_TX_1519_MAXB_FRAMES", 0x934, 0 },
|
|
{ "XGM_STAT_TX_ERR_FRAMES", 0x938, 0 },
|
|
{ "XGM_STAT_RX_BYTES_LOW", 0x93c, 0 },
|
|
{ "XGM_STAT_RX_BYTES_HIGH", 0x940, 0 },
|
|
{ "RxBytes_high", 0, 13 },
|
|
{ "XGM_STAT_RX_FRAMES_LOW", 0x944, 0 },
|
|
{ "XGM_STAT_RX_FRAMES_HIGH", 0x948, 0 },
|
|
{ "RxFrames_high", 0, 4 },
|
|
{ "XGM_STAT_RX_BCAST_FRAMES", 0x94c, 0 },
|
|
{ "XGM_STAT_RX_MCAST_FRAMES", 0x950, 0 },
|
|
{ "XGM_STAT_RX_PAUSE_FRAMES", 0x954, 0 },
|
|
{ "RxPauseFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_64B_FRAMES", 0x958, 0 },
|
|
{ "XGM_STAT_RX_65_127B_FRAMES", 0x95c, 0 },
|
|
{ "XGM_STAT_RX_128_255B_FRAMES", 0x960, 0 },
|
|
{ "XGM_STAT_RX_256_511B_FRAMES", 0x964, 0 },
|
|
{ "XGM_STAT_RX_512_1023B_FRAMES", 0x968, 0 },
|
|
{ "XGM_STAT_RX_1024_1518B_FRAMES", 0x96c, 0 },
|
|
{ "XGM_STAT_RX_1519_MAXB_FRAMES", 0x970, 0 },
|
|
{ "XGM_STAT_RX_SHORT_FRAMES", 0x974, 0 },
|
|
{ "RxShortFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_OVERSIZE_FRAMES", 0x978, 0 },
|
|
{ "RxOversizeFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_JABBER_FRAMES", 0x97c, 0 },
|
|
{ "RxJabberFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_CRC_ERR_FRAMES", 0x980, 0 },
|
|
{ "RxCRCErrFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_LENGTH_ERR_FRAMES", 0x984, 0 },
|
|
{ "RxLengthErrFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0x988, 0 },
|
|
{ "RxSymCodeErrFrames", 0, 16 },
|
|
{ "XGM_XAUI_PCS_ERR", 0x998, 0 },
|
|
{ "PCS_SyncStatus", 5, 4 },
|
|
{ "PCS_CTCFIFOErr", 1, 4 },
|
|
{ "PCS_NotAligned", 0, 1 },
|
|
{ "XGM_RGMII_STATUS", 0x99c, 0 },
|
|
{ "GMIIDuplex", 3, 1 },
|
|
{ "GMIISpeed", 1, 2 },
|
|
{ "GMIILinkStatus", 0, 1 },
|
|
{ "XGM_WOL_STATUS", 0x9a0, 0 },
|
|
{ "PatDetected", 31, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGM_RX_MAX_PKT_SIZE_ERR_CNT", 0x9a4, 0 },
|
|
{ "XGM_TX_SPI4_SOP_EOP_CNT", 0x9a8, 0 },
|
|
{ "TxSPI4SopCnt", 16, 16 },
|
|
{ "TxSPI4EopCnt", 0, 16 },
|
|
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0x9ac, 0 },
|
|
{ "RxSPI4SopCnt", 16, 16 },
|
|
{ "RxSPI4EopCnt", 0, 16 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|
|
struct reg_info t3c_xgmac0_1_regs[] = {
|
|
{ "XGM_TX_CTRL", 0xa00, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGM_TX_CFG", 0xa04, 0 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGM_TX_PAUSE_QUANTA", 0xa08, 0 },
|
|
{ "TxPauseQuanta", 0, 16 },
|
|
{ "XGM_RX_CTRL", 0xa0c, 0 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "XGM_RX_CFG", 0xa10, 0 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGM_RX_HASH_LOW", 0xa14, 0 },
|
|
{ "XGM_RX_HASH_HIGH", 0xa18, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_1", 0xa1c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_1", 0xa20, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_2", 0xa24, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_2", 0xa28, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_3", 0xa2c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_3", 0xa30, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_4", 0xa34, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_4", 0xa38, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_5", 0xa3c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_5", 0xa40, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_6", 0xa44, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_6", 0xa48, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_7", 0xa4c, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_7", 0xa50, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_EXACT_MATCH_LOW_8", 0xa54, 0 },
|
|
{ "XGM_RX_EXACT_MATCH_HIGH_8", 0xa58, 0 },
|
|
{ "address_high", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_1", 0xa5c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_2", 0xa60, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_3", 0xa64, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_RX_TYPE_MATCH_4", 0xa68, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGM_INT_STATUS", 0xa6c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_MASK", 0xa70, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_ENABLE", 0xa74, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_XGM_INT_DISABLE", 0xa78, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGM_TX_PAUSE_TIMER", 0xa7c, 0 },
|
|
{ "CurPauseTimer", 0, 16 },
|
|
{ "XGM_STAT_CTRL", 0xa80, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGM_RXFIFO_CFG", 0xa84, 0 },
|
|
{ "RxFIFO_empty", 31, 1 },
|
|
{ "RxFIFO_full", 30, 1 },
|
|
{ "RxFIFOPauseHWM", 17, 12 },
|
|
{ "RxFIFOPauseLWM", 5, 12 },
|
|
{ "ForcedPause", 4, 1 },
|
|
{ "ExternLoopback", 3, 1 },
|
|
{ "RxByteSwap", 2, 1 },
|
|
{ "RxStrFrwrd", 1, 1 },
|
|
{ "DisErrFrames", 0, 1 },
|
|
{ "XGM_TXFIFO_CFG", 0xa88, 0 },
|
|
{ "TxFIFO_empty", 31, 1 },
|
|
{ "TxFIFO_full", 30, 1 },
|
|
{ "UnderunFix", 22, 1 },
|
|
{ "EnDropPkt", 21, 1 },
|
|
{ "TxIPG", 13, 8 },
|
|
{ "TxFIFOThresh", 4, 9 },
|
|
{ "InternLoopback", 3, 1 },
|
|
{ "TxByteSwap", 2, 1 },
|
|
{ "DisCRC", 1, 1 },
|
|
{ "DisPreAmble", 0, 1 },
|
|
{ "XGM_SLOW_TIMER", 0xa8c, 0 },
|
|
{ "PauseSlowTimerEn", 31, 1 },
|
|
{ "PauseSlowTimer", 0, 20 },
|
|
{ "XGM_PAUSE_TIMER", 0xa90, 0 },
|
|
{ "PauseTimer", 0, 20 },
|
|
{ "XGM_XAUI_PCS_TEST", 0xa94, 0 },
|
|
{ "TestPattern", 1, 2 },
|
|
{ "EnTest", 0, 1 },
|
|
{ "XGM_RGMII_CTRL", 0xa98, 0 },
|
|
{ "PhAlignFIFOThresh", 1, 2 },
|
|
{ "TxClk90Shift", 0, 1 },
|
|
{ "XGM_RGMII_IMP", 0xa9c, 0 },
|
|
{ "CalReset", 8, 1 },
|
|
{ "CalUpdate", 7, 1 },
|
|
{ "ImpSetUpdate", 6, 1 },
|
|
{ "RGMIIImpPD", 3, 3 },
|
|
{ "RGMIIImpPU", 0, 3 },
|
|
{ "XGM_RX_MAX_PKT_SIZE", 0xaa8, 0 },
|
|
{ "RxMaxFramerSize", 17, 14 },
|
|
{ "RxEnErrorGather", 16, 1 },
|
|
{ "RxEnSingleFlit", 15, 1 },
|
|
{ "RxEnFramer", 14, 1 },
|
|
{ "RxMaxPktSize", 0, 14 },
|
|
{ "XGM_RESET_CTRL", 0xaac, 0 },
|
|
{ "XGMAC_STOP_EN", 4, 1 },
|
|
{ "XG2G_Reset_", 3, 1 },
|
|
{ "RGMII_Reset_", 2, 1 },
|
|
{ "PCS_Reset_", 1, 1 },
|
|
{ "MAC_Reset_", 0, 1 },
|
|
{ "XGM_XAUI1G_CTRL", 0xab0, 0 },
|
|
{ "XAUI1GLinkId", 0, 2 },
|
|
{ "XGM_SERDES_LANE_CTRL", 0xab4, 0 },
|
|
{ "LaneReversal", 8, 1 },
|
|
{ "TxPolarity", 4, 4 },
|
|
{ "RxPolarity", 0, 4 },
|
|
{ "XGM_PORT_CFG", 0xab8, 0 },
|
|
{ "SafeSpeedChange", 4, 1 },
|
|
{ "ClkDivReset_", 3, 1 },
|
|
{ "PortSpeed", 1, 2 },
|
|
{ "EnRGMII", 0, 1 },
|
|
{ "XGM_EPIO_DATA0", 0xac0, 0 },
|
|
{ "XGM_EPIO_DATA1", 0xac4, 0 },
|
|
{ "XGM_EPIO_DATA2", 0xac8, 0 },
|
|
{ "XGM_EPIO_DATA3", 0xacc, 0 },
|
|
{ "XGM_EPIO_OP", 0xad0, 0 },
|
|
{ "PIO_Ready", 31, 1 },
|
|
{ "PIO_WrRd", 24, 1 },
|
|
{ "PIO_Address", 0, 8 },
|
|
{ "XGM_INT_ENABLE", 0xad4, 0 },
|
|
{ "XAUIPCSDECErr", 24, 1 },
|
|
{ "RGMIIRxFIFOOverflow", 23, 1 },
|
|
{ "RGMIIRxFIFOUnderflow", 22, 1 },
|
|
{ "RxPktSizeError", 21, 1 },
|
|
{ "WOLPatDetected", 20, 1 },
|
|
{ "TXFIFO_prty_err", 17, 3 },
|
|
{ "RXFIFO_prty_err", 14, 3 },
|
|
{ "TXFIFO_underrun", 13, 1 },
|
|
{ "RXFIFO_overflow", 12, 1 },
|
|
{ "SERDESBISTErr", 8, 4 },
|
|
{ "SERDESLowSigChange", 4, 4 },
|
|
{ "XAUIPCSCTCErr", 3, 1 },
|
|
{ "XAUIPCSAlignChange", 2, 1 },
|
|
{ "RGMIILinkStsChange", 1, 1 },
|
|
{ "xgm_int", 0, 1 },
|
|
{ "XGM_INT_CAUSE", 0xad8, 0 },
|
|
{ "XAUIPCSDECErr", 24, 1 },
|
|
{ "RGMIIRxFIFOOverflow", 23, 1 },
|
|
{ "RGMIIRxFIFOUnderflow", 22, 1 },
|
|
{ "RxPktSizeError", 21, 1 },
|
|
{ "WOLPatDetected", 20, 1 },
|
|
{ "TXFIFO_prty_err", 17, 3 },
|
|
{ "RXFIFO_prty_err", 14, 3 },
|
|
{ "TXFIFO_underrun", 13, 1 },
|
|
{ "RXFIFO_overflow", 12, 1 },
|
|
{ "SERDESBISTErr", 8, 4 },
|
|
{ "SERDESLowSigChange", 4, 4 },
|
|
{ "XAUIPCSCTCErr", 3, 1 },
|
|
{ "XAUIPCSAlignChange", 2, 1 },
|
|
{ "RGMIILinkStsChange", 1, 1 },
|
|
{ "xgm_int", 0, 1 },
|
|
{ "XGM_XAUI_ACT_CTRL", 0xadc, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "XGM_SERDES_CTRL0", 0xae0, 0 },
|
|
{ "IntSerLPBK3", 27, 1 },
|
|
{ "IntSerLPBK2", 26, 1 },
|
|
{ "IntSerLPBK1", 25, 1 },
|
|
{ "IntSerLPBK0", 24, 1 },
|
|
{ "Reset3", 23, 1 },
|
|
{ "Reset2", 22, 1 },
|
|
{ "Reset1", 21, 1 },
|
|
{ "Reset0", 20, 1 },
|
|
{ "Pwrdn3", 19, 1 },
|
|
{ "Pwrdn2", 18, 1 },
|
|
{ "Pwrdn1", 17, 1 },
|
|
{ "Pwrdn0", 16, 1 },
|
|
{ "ResetPLL23", 15, 1 },
|
|
{ "ResetPLL01", 14, 1 },
|
|
{ "PW23", 12, 2 },
|
|
{ "PW01", 10, 2 },
|
|
{ "Deq", 6, 4 },
|
|
{ "Dtx", 2, 4 },
|
|
{ "LoDrv", 1, 1 },
|
|
{ "HiDrv", 0, 1 },
|
|
{ "XGM_SERDES_CTRL1", 0xae4, 0 },
|
|
{ "FmOffset3", 19, 5 },
|
|
{ "FmOffsetEn3", 18, 1 },
|
|
{ "FmOffset2", 13, 5 },
|
|
{ "FmOffsetEn2", 12, 1 },
|
|
{ "FmOffset1", 7, 5 },
|
|
{ "FmOffsetEn1", 6, 1 },
|
|
{ "FmOffset0", 1, 5 },
|
|
{ "FmOffsetEn0", 0, 1 },
|
|
{ "XGM_SERDES_CTRL2", 0xae8, 0 },
|
|
{ "DnIn3", 11, 1 },
|
|
{ "UpIn3", 10, 1 },
|
|
{ "RxSlave3", 9, 1 },
|
|
{ "DnIn2", 8, 1 },
|
|
{ "UpIn2", 7, 1 },
|
|
{ "RxSlave2", 6, 1 },
|
|
{ "DnIn1", 5, 1 },
|
|
{ "UpIn1", 4, 1 },
|
|
{ "RxSlave1", 3, 1 },
|
|
{ "DnIn0", 2, 1 },
|
|
{ "UpIn0", 1, 1 },
|
|
{ "RxSlave0", 0, 1 },
|
|
{ "XGM_SERDES_CTRL3", 0xaec, 0 },
|
|
{ "ExtBISTChkErrClr3", 31, 1 },
|
|
{ "ExtBISTChkEn3", 30, 1 },
|
|
{ "ExtBISTGenEn3", 29, 1 },
|
|
{ "ExtBISTPat3", 26, 3 },
|
|
{ "ExtParReset3", 25, 1 },
|
|
{ "ExtParLPBK3", 24, 1 },
|
|
{ "ExtBISTChkErrClr2", 23, 1 },
|
|
{ "ExtBISTChkEn2", 22, 1 },
|
|
{ "ExtBISTGenEn2", 21, 1 },
|
|
{ "ExtBISTPat2", 18, 3 },
|
|
{ "ExtParReset2", 17, 1 },
|
|
{ "ExtParLPBK2", 16, 1 },
|
|
{ "ExtBISTChkErrClr1", 15, 1 },
|
|
{ "ExtBISTChkEn1", 14, 1 },
|
|
{ "ExtBISTGenEn1", 13, 1 },
|
|
{ "ExtBISTPat1", 10, 3 },
|
|
{ "ExtParReset1", 9, 1 },
|
|
{ "ExtParLPBK1", 8, 1 },
|
|
{ "ExtBISTChkErrClr0", 7, 1 },
|
|
{ "ExtBISTChkEn0", 6, 1 },
|
|
{ "ExtBISTGenEn0", 5, 1 },
|
|
{ "ExtBISTPat0", 2, 3 },
|
|
{ "ExtParReset0", 1, 1 },
|
|
{ "ExtParLPBK0", 0, 1 },
|
|
{ "XGM_SERDES_STAT0", 0xaf0, 0 },
|
|
{ "ExtBISTChkErrCnt0", 4, 24 },
|
|
{ "ExtBISTChkFmd0", 3, 1 },
|
|
{ "LowSigForceEn0", 2, 1 },
|
|
{ "LowSigForceValue0", 1, 1 },
|
|
{ "LowSig0", 0, 1 },
|
|
{ "XGM_SERDES_STAT1", 0xaf4, 0 },
|
|
{ "ExtBISTChkErrCnt1", 4, 24 },
|
|
{ "ExtBISTChkFmd1", 3, 1 },
|
|
{ "LowSigForceEn1", 2, 1 },
|
|
{ "LowSigForceValue1", 1, 1 },
|
|
{ "LowSig1", 0, 1 },
|
|
{ "XGM_SERDES_STAT2", 0xaf8, 0 },
|
|
{ "ExtBISTChkErrCnt2", 4, 24 },
|
|
{ "ExtBISTChkFmd2", 3, 1 },
|
|
{ "LowSigForceEn2", 2, 1 },
|
|
{ "LowSigForceValue2", 1, 1 },
|
|
{ "LowSig2", 0, 1 },
|
|
{ "XGM_SERDES_STAT3", 0xafc, 0 },
|
|
{ "ExtBISTChkErrCnt3", 4, 24 },
|
|
{ "ExtBISTChkFmd3", 3, 1 },
|
|
{ "LowSigForceEn3", 2, 1 },
|
|
{ "LowSigForceValue3", 1, 1 },
|
|
{ "LowSig3", 0, 1 },
|
|
{ "XGM_STAT_TX_BYTE_LOW", 0xb00, 0 },
|
|
{ "XGM_STAT_TX_BYTE_HIGH", 0xb04, 0 },
|
|
{ "TxBytes_high", 0, 13 },
|
|
{ "XGM_STAT_TX_FRAME_LOW", 0xb08, 0 },
|
|
{ "XGM_STAT_TX_FRAME_HIGH", 0xb0c, 0 },
|
|
{ "TxFrames_high", 0, 4 },
|
|
{ "XGM_STAT_TX_BCAST", 0xb10, 0 },
|
|
{ "XGM_STAT_TX_MCAST", 0xb14, 0 },
|
|
{ "XGM_STAT_TX_PAUSE", 0xb18, 0 },
|
|
{ "XGM_STAT_TX_64B_FRAMES", 0xb1c, 0 },
|
|
{ "XGM_STAT_TX_65_127B_FRAMES", 0xb20, 0 },
|
|
{ "XGM_STAT_TX_128_255B_FRAMES", 0xb24, 0 },
|
|
{ "XGM_STAT_TX_256_511B_FRAMES", 0xb28, 0 },
|
|
{ "XGM_STAT_TX_512_1023B_FRAMES", 0xb2c, 0 },
|
|
{ "XGM_STAT_TX_1024_1518B_FRAMES", 0xb30, 0 },
|
|
{ "XGM_STAT_TX_1519_MAXB_FRAMES", 0xb34, 0 },
|
|
{ "XGM_STAT_TX_ERR_FRAMES", 0xb38, 0 },
|
|
{ "XGM_STAT_RX_BYTES_LOW", 0xb3c, 0 },
|
|
{ "XGM_STAT_RX_BYTES_HIGH", 0xb40, 0 },
|
|
{ "RxBytes_high", 0, 13 },
|
|
{ "XGM_STAT_RX_FRAMES_LOW", 0xb44, 0 },
|
|
{ "XGM_STAT_RX_FRAMES_HIGH", 0xb48, 0 },
|
|
{ "RxFrames_high", 0, 4 },
|
|
{ "XGM_STAT_RX_BCAST_FRAMES", 0xb4c, 0 },
|
|
{ "XGM_STAT_RX_MCAST_FRAMES", 0xb50, 0 },
|
|
{ "XGM_STAT_RX_PAUSE_FRAMES", 0xb54, 0 },
|
|
{ "RxPauseFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_64B_FRAMES", 0xb58, 0 },
|
|
{ "XGM_STAT_RX_65_127B_FRAMES", 0xb5c, 0 },
|
|
{ "XGM_STAT_RX_128_255B_FRAMES", 0xb60, 0 },
|
|
{ "XGM_STAT_RX_256_511B_FRAMES", 0xb64, 0 },
|
|
{ "XGM_STAT_RX_512_1023B_FRAMES", 0xb68, 0 },
|
|
{ "XGM_STAT_RX_1024_1518B_FRAMES", 0xb6c, 0 },
|
|
{ "XGM_STAT_RX_1519_MAXB_FRAMES", 0xb70, 0 },
|
|
{ "XGM_STAT_RX_SHORT_FRAMES", 0xb74, 0 },
|
|
{ "RxShortFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_OVERSIZE_FRAMES", 0xb78, 0 },
|
|
{ "RxOversizeFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_JABBER_FRAMES", 0xb7c, 0 },
|
|
{ "RxJabberFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_CRC_ERR_FRAMES", 0xb80, 0 },
|
|
{ "RxCRCErrFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_LENGTH_ERR_FRAMES", 0xb84, 0 },
|
|
{ "RxLengthErrFrames", 0, 16 },
|
|
{ "XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0xb88, 0 },
|
|
{ "RxSymCodeErrFrames", 0, 16 },
|
|
{ "XGM_XAUI_PCS_ERR", 0xb98, 0 },
|
|
{ "PCS_SyncStatus", 5, 4 },
|
|
{ "PCS_CTCFIFOErr", 1, 4 },
|
|
{ "PCS_NotAligned", 0, 1 },
|
|
{ "XGM_RGMII_STATUS", 0xb9c, 0 },
|
|
{ "GMIIDuplex", 3, 1 },
|
|
{ "GMIISpeed", 1, 2 },
|
|
{ "GMIILinkStatus", 0, 1 },
|
|
{ "XGM_WOL_STATUS", 0xba0, 0 },
|
|
{ "PatDetected", 31, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGM_RX_MAX_PKT_SIZE_ERR_CNT", 0xba4, 0 },
|
|
{ "XGM_TX_SPI4_SOP_EOP_CNT", 0xba8, 0 },
|
|
{ "TxSPI4SopCnt", 16, 16 },
|
|
{ "TxSPI4EopCnt", 0, 16 },
|
|
{ "XGM_RX_SPI4_SOP_EOP_CNT", 0xbac, 0 },
|
|
{ "RxSPI4SopCnt", 16, 16 },
|
|
{ "RxSPI4EopCnt", 0, 16 },
|
|
{ NULL, 0, 0 }
|
|
};
|
|
|