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It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized. Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf |
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aim | ||
booke | ||
compile | ||
conf | ||
cpufreq | ||
fpu | ||
include | ||
mpc85xx | ||
ofw | ||
powermac | ||
powerpc | ||
psim |