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b14d7dac8a
- Separate bus dependent part and independent part. - Moved source files to sys/dev/fe (repo copied). - Fixed some comments by chi@bd.mbn.or.jp (Chiharu Shibata) Tested by: bsd-nomads@clave.gr.jp and FreeBSD98-testers@jp.freebsd.org
167 lines
5.6 KiB
C
167 lines
5.6 KiB
C
/*
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* Hardware specification of various 8696x based Ethernet cards.
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* Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>
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*
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* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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*
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* This software may be used, modified, copied, distributed, and sold,
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* in both source and binary form provided that the above copyright,
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* these terms and the following disclaimer are retained. The name of
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* the author and/or the contributor may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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/*
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* Registers on FMV-180 series' ISA bus interface ASIC.
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* I'm not sure the following register names are appropriate.
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* Doesn't it look silly, eh? FIXME.
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*/
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#define FE_FMV0 16 /* Card status register #0 */
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#define FE_FMV1 17 /* Card status register #1 */
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#define FE_FMV2 18 /* Card config register #0 */
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#define FE_FMV3 19 /* Card config register #1 */
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#define FE_FMV4 20 /* Station address #1 */
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#define FE_FMV5 21 /* Station address #2 */
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#define FE_FMV6 22 /* Station address #3 */
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#define FE_FMV7 23 /* Station address #4 */
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#define FE_FMV8 24 /* Station address #5 */
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#define FE_FMV9 25 /* Station address #6 */
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#define FE_FMV10 26 /* Buffer RAM control register */
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#define FE_FMV11 27 /* Buffer RAM data register */
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/*
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* FMV-180 series' ASIC register values.
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*/
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/* FMV0: Card status register #0: Misc info? */
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#define FE_FMV0_MEDIA 0x07 /* Supported physical media. */
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#define FE_FMV0_PRRDY 0x10 /* ??? */
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#define FE_FMV0_PRERR 0x20 /* ??? */
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#define FE_FMV0_ERRDY 0x40 /* ??? */
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#define FE_FMV0_IREQ 0x80 /* ??? */
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#define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */
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#define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */
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#define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */
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/* Card status register #1: Hardware revision. */
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#define FE_FMV1_REV 0x0F /* Card revision */
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#define FE_FMV1_UPPER 0xF0 /* Usage unknown */
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/* Card config register #0: I/O port address assignment. */
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#define FE_FMV2_IOS 0x07 /* I/O selection. */
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#define FE_FMV2_MES 0x38 /* ??? boot ROM? */
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#define FE_FMV2_IRS 0xC0 /* IRQ selection. */
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#define FE_FMV2_IOS_SHIFT 0
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#define FE_FMV2_MES_SHIFT 3
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#define FE_FMV2_IRS_SHIFT 6
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/* Card config register #1: IRQ enable */
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#define FE_FMV3_IRQENB 0x80 /* IRQ enable. */
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/*
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* Register(?) specific to AT1700/RE2000.
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*/
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#define FE_ATI_RESET 0x1F /* Write to reset the 86965. */
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/* EEPROM allocation (offsets) of AT1700/RE2000. */
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#define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */
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#define FE_ATI_EEP_MEDIA 0x18 /* Media type. */
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#define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */
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#define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */
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#define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */
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/* Value for FE_ATI_EEP_MODEL. */
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#define FE_ATI_MODEL_AT1700T 0x00
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#define FE_ATI_MODEL_AT1700BT 0x01
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#define FE_ATI_MODEL_AT1700FT 0x02
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#define FE_ATI_MODEL_AT1700AT 0x03
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/*
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* Registers on MBH10302.
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*/
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#define FE_MBH0 0x10 /* ??? Including interrupt. */
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#define FE_MBH1 0x11 /* ??? */
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#define FE_MBH10 0x1A /* Station address. (10 - 15) */
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/* Values to be set in MBH0 register. */
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#define FE_MBH0_MAGIC 0x0D /* Just a magic constant? */
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#define FE_MBH0_INTR 0x10 /* Master interrupt control. */
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#define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */
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#define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */
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/*
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* Registers on RE1000. (*NOT* on RE1000 Plus.)
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*/
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/* IRQ configuration. */
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#define FE_RE1000_IRQCONF 0x10
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/*
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* Fujitsu MB86965 JLI mode support routines.
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*/
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/* Datasheet for 86965 explicitly states that it only supports serial
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* EEPROM with 16 words (32 bytes) capacity. (I.e., 93C06.) However,
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* ones with 64 words (128 bytes) are available in the marked, namely
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* 93C46, and are also fully compatible with 86965. It is known that
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* some boards (e.g., ICL) actually have 93C46 on them and use extra
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* storage to keep various config info. */
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#define JLI_EEPROM_SIZE 128
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/*
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* SSi 78Q8377A support routines.
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*/
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#define SSI_EEPROM_SIZE 512
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#define SSI_DIN 0x01
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#define SSI_DAT 0x01
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#define SSI_CSL 0x02
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#define SSI_CLK 0x04
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#define SSI_EEP 0x10
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#define FE_SSI_EEP_IRQ 9 /* Irq ??? */
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#define FE_SSI_EEP_ADDR 16 /* Station(MAC) address */
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#define FE_SSI_EEP_DUPLEX 25 /* Duplex mode ??? */
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/*
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* TDK/LANX boards support routines.
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*/
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/* AX012/AX013 equips an X24C01 chip, which has 128 bytes of memory cells. */
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#define LNX_EEPROM_SIZE 128
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/* Bit assignments and command definitions for the serial EEPROM
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interface register in LANX ASIC. */
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#define LNX_SDA_HI 0x08 /* Drive SDA line high (logical 1.) */
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#define LNX_SDA_LO 0x00 /* Drive SDA line low (logical 0.) */
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#define LNX_SDA_FL 0x08 /* Float (don't drive) SDA line. */
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#define LNX_SDA_IN 0x01 /* Mask for reading SDA line. */
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#define LNX_CLK_HI 0x04 /* Drive clock line high (active.) */
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#define LNX_CLK_LO 0x00 /* Drive clock line low (inactive.) */
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