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in each cycle, with a tunable max cycle count defined in fdreg.h. This is said to fix the problem on some Compaq hardware (and perhaps on other machines using the Natsemi PC87317 chip) where the fdc(4) driver failed to operate at all. PR: kern/21397 Submitted by: Jung-uk Kim <jkim@niksun.com> MFC after: 3 days
84 lines
3.6 KiB
C
84 lines
3.6 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91
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* $FreeBSD$
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*/
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/*
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* AT floppy controller registers and bitfields
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*/
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/* uses NEC765 controller */
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#include <dev/ic/nec765.h>
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/* registers */
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#define FDOUT 2 /* Digital Output Register (W) */
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#define FDO_FDSEL 0x03 /* floppy device select */
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#define FDO_FRST 0x04 /* floppy controller reset */
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#define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */
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#define FDO_MOEN0 0x10 /* motor enable drive 0 */
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#define FDO_MOEN1 0x20 /* motor enable drive 1 */
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#define FDO_MOEN2 0x40 /* motor enable drive 2 */
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#define FDO_MOEN3 0x80 /* motor enable drive 3 */
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#define FDSTS 4 /* NEC 765 Main Status Register (R) */
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#define FDDATA 5 /* NEC 765 Data Register (R/W) */
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#define FDCTL 7 /* Control Register (W) */
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/*
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* The definitions for FDC_500KBPS etc. have been moved out to <sys/fdcio.h>
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* since they need to be visible in userland. They cover the lower two bits
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* of FDCTL when used for output.
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*/
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/*
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* this is the secret PIO data port (offset from base)
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*/
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#define FDC_YE_DATAPORT 6
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#define FDIN 7 /* Digital Input Register (R) */
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#define FDI_DCHG 0x80 /* diskette has been changed */
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/* requires drive and motor being selected */
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/* is cleared by any step pulse to drive */
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/*
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* Timeout value for the PIO loops to wait until the FDC main status
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* register matches our expextations (request for master, direction
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* bit). This is the number of cycles to loop while waiting, with a
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* 1-microsecond (in theory) DELAY() in each cycle. In particular on
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* slower hardware, it could take a fair amount more to execute. Of
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* course, as soon as the FDC main status register indicates the correct
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* bits are set, the loop will terminate, so this is merely a safety
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* measure to avoid looping forever in case of broken hardware.
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*/
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#define FDSTS_TIMEOUT 200
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