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580 lines
13 KiB
C
580 lines
13 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD
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* $FreeBSD$
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*/
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#ifndef __MIPS_EXTS_H__
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#define __MIPS_EXTS_H__
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#define CPU_BLOCKID_IFU 0
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#define CPU_BLOCKID_ICU 1
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#define CPU_BLOCKID_IEU 2
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#define CPU_BLOCKID_LSU 3
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#define CPU_BLOCKID_MMU 4
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#define CPU_BLOCKID_PRF 5
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#define LSU_CERRLOG_REGID 9
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#if defined(__mips_n64) || defined(__mips_n32)
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static __inline uint64_t
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read_xlr_ctrl_register(int block, int reg)
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{
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uint64_t res;
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $9, %1\n\t"
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".word 0x71280018\n\t" /* mfcr $8, $9 */
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"move %0, $8\n\t"
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".set pop\n"
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: "=r" (res) : "r"((block << 8) | reg)
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: "$8", "$9"
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);
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return (res);
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}
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static __inline void
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write_xlr_ctrl_register(int block, int reg, uint64_t value)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $8, %0\n"
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"move $9, %1\n"
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".word 0x71280019\n" /* mtcr $8, $9 */
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".set pop\n"
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:
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: "r" (value), "r" ((block << 8) | reg)
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: "$8", "$9"
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);
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}
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#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
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static __inline uint64_t
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read_xlr_ctrl_register(int block, int reg)
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{
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uint32_t high, low;
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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".set mips64\n\t"
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"move $9, %2\n"
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".word 0x71280018\n" /* "mfcr $8, $9\n" */
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"dsra32 %0, $8, 0\n\t"
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"sll %1, $8, 0\n\t"
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".set pop"
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: "=r" (high), "=r"(low)
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: "r" ((block << 8) | reg)
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: "$8", "$9");
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return ( (((uint64_t)high) << 32) | low);
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}
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static __inline void
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write_xlr_ctrl_register(int block, int reg, uint64_t value)
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{
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uint32_t low, high;
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high = value >> 32;
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low = value & 0xffffffff;
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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".set mips64\n\t"
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"dsll32 $9, %0, 0\n\t"
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"dsll32 $8, %1, 0\n\t"
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"dsrl32 $8, $8, 0\n\t"
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"or $8, $9, $8\n\t"
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"move $9, %2\n\t"
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".word 0x71280019\n\t" /* mtcr $8, $9 */
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".set pop\n"
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: /* No outputs */
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: "r" (high), "r" (low), "r"((block << 8) | reg)
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: "$8", "$9");
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}
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#endif /* defined(__mips_n64) || defined(__mips_n32) */
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/*
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* 32 bit read write for c0
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*/
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#define read_c0_register32(reg, sel) \
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({ \
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uint32_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mfc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c0_register32(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mtc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#define read_c2_register32(reg, sel) \
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({ \
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uint32_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mfc2 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c2_register32(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips32\n\t" \
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"mtc2 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#if defined(__mips_n64) || defined(__mips_n32)
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/*
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* On 64 bit compilation, the operations are simple
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*/
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#define read_c0_register64(reg, sel) \
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({ \
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uint64_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmfc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c0_register64(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmtc0 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#define read_c2_register64(reg, sel) \
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({ \
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uint64_t __rv; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmfc2 %0, $%1, %2\n\t" \
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".set pop\n" \
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: "=r" (__rv) : "i" (reg), "i" (sel) ); \
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__rv; \
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})
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#define write_c2_register64(reg, sel, value) \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set mips64\n\t" \
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"dmtc2 %0, $%1, %2\n\t" \
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".set pop\n" \
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: : "r" (value), "i" (reg), "i" (sel) );
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#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
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/*
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* 32 bit compilation, 64 bit values has to split
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*/
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#define read_c0_register64(reg, sel) \
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({ \
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uint32_t __high, __low; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dmfc0 $8, $%2, %3\n\t" \
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"dsra32 %0, $8, 0\n\t" \
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"sll %1, $8, 0\n\t" \
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".set pop\n" \
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: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
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: "$8"); \
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((uint64_t)__high << 32) | __low; \
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})
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#define write_c0_register64(reg, sel, value) \
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do { \
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uint32_t __high = value >> 32; \
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uint32_t __low = value & 0xffffffff; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dsll32 $8, %1, 0\n\t" \
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"dsll32 $9, %0, 0\n\t" \
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"dsrl32 $8, $8, 0\n\t" \
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"or $8, $8, $9\n\t" \
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"dmtc0 $8, $%2, %3\n\t" \
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".set pop" \
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:: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
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:"$8", "$9"); \
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} while(0)
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#define read_c2_register64(reg, sel) \
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({ \
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uint32_t __high, __low; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dmfc2 $8, $%2, %3\n\t" \
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"dsra32 %0, $8, 0\n\t" \
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"sll %1, $8, 0\n\t" \
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".set pop\n" \
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: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
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: "$8"); \
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((uint64_t)__high << 32) | __low; \
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})
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#define write_c2_register64(reg, sel, value) \
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do { \
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uint32_t __high = value >> 32; \
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uint32_t __low = value & 0xffffffff; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips64\n\t" \
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"dsll32 $8, %1, 0\n\t" \
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"dsll32 $9, %0, 0\n\t" \
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"dsrl32 $8, $8, 0\n\t" \
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"or $8, $8, $9\n\t" \
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"dmtc2 $8, $%2, %3\n\t" \
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".set pop" \
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:: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
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:"$8", "$9"); \
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} while(0)
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#endif /* defined(__mips_n64) || defined(__mips_n32) */
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static __inline int
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xlr_cpu_id(void)
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{
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return (read_c0_register32(15, 1) & 0x1f);
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}
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static __inline int
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xlr_core_id(void)
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{
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return (xlr_cpu_id() / 4);
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}
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static __inline int
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xlr_thr_id(void)
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{
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return (read_c0_register32(15, 1) & 0x3);
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}
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/* Additional registers on the XLR */
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#define MIPS_COP_0_OSSCRATCH 22
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#define XLR_CACHELINE_SIZE 32
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/* functions to write to and read from the extended
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* cp0 registers.
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* EIRR : Extended Interrupt Request Register
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* cp0 register 9 sel 6
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* bits 0...7 are same as cause register 8...15
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* EIMR : Extended Interrupt Mask Register
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* cp0 register 9 sel 7
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* bits 0...7 are same as status register 8...15
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*/
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static __inline uint64_t
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read_c0_eirr64(void)
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{
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return (read_c0_register64(9, 6));
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}
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static __inline void
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write_c0_eirr64(uint64_t val)
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{
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write_c0_register64(9, 6, val);
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}
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static __inline uint64_t
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read_c0_eimr64(void)
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{
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return (read_c0_register64(9, 7));
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}
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static __inline void
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write_c0_eimr64(uint64_t val)
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{
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write_c0_register64(9, 7, val);
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}
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static __inline int
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xlr_test_and_set(int *lock)
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{
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int oldval = 0;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"li $8, 1\n"
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// "swapw $8, $9\n"
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".word 0x71280014\n"
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"move %1, $8\n"
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".set pop\n"
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: "+m"(*lock), "=r"(oldval)
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: "r"((unsigned long)lock)
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: "$8", "$9"
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);
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return (oldval == 0 ? 1 /* success */ : 0 /* failure */);
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}
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static __inline uint32_t
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xlr_mfcr(uint32_t reg)
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{
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uint32_t val;
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__asm__ __volatile__(
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"move $8, %1\n"
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".word 0x71090018\n"
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"move %0, $9\n"
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: "=r"(val)
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: "r"(reg):"$8", "$9");
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return val;
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}
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static __inline void
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xlr_mtcr(uint32_t reg, uint32_t val)
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{
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__asm__ __volatile__(
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"move $8, %1\n"
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"move $9, %0\n"
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".word 0x71090019\n"
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:: "r"(val), "r"(reg)
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: "$8", "$9");
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}
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/*
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* Atomic increment a unsigned int
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*/
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static __inline unsigned int
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xlr_ldaddwu(unsigned int value, unsigned int *addr)
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{
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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"move $8, %2\n"
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"move $9, %3\n"
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".word 0x71280011\n" /* ldaddwu $8, $9 */
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"move %0, $8\n"
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".set pop\n"
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: "=&r"(value), "+m"(*addr)
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: "0"(value), "r" ((unsigned long)addr)
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: "$8", "$9");
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return (value);
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}
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#if defined(__mips_n64)
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static __inline uint32_t
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xlr_paddr_lw(uint64_t paddr)
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{
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paddr |= 0x9800000000000000ULL;
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return (*(uint32_t *)(uintptr_t)paddr);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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paddr |= 0x9800000000000000ULL;
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return (*(uint64_t *)(uintptr_t)paddr);
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}
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#elif defined(__mips_n32)
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static __inline uint32_t
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xlr_paddr_lw(uint64_t paddr)
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{
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uint32_t val;
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paddr |= 0x9800000000000000ULL;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"lw %0, 0(%1) \n\t"
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".set pop \n"
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: "=r"(val)
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: "r"(paddr));
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return (val);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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uint64_t val;
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paddr |= 0x9800000000000000ULL;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"ld %0, 0(%1) \n\t"
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".set pop \n"
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: "=r"(val)
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: "r"(paddr));
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return (val);
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}
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#else /* o32 compilation */
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static __inline uint32_t
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xlr_paddr_lw(uint64_t paddr)
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{
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uint32_t addrh, addrl;
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uint32_t val;
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addrh = 0x98000000 | (paddr >> 32);
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addrl = paddr & 0xffffffff;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"dsll32 $8, %1, 0 \n\t"
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"dsll32 $9, %2, 0 \n\t" /* get rid of the */
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"dsrl32 $9, $9, 0 \n\t" /* sign extend */
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"or $9, $8, $8 \n\t"
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"lw %0, 0($9) \n\t"
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".set pop \n"
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: "=r"(val)
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: "r"(addrh), "r"(addrl)
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: "$8", "$9");
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return (val);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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uint32_t addrh, addrl;
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uint32_t valh, vall;
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addrh = 0x98000000 | (paddr >> 32);
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addrl = paddr & 0xffffffff;
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__asm__ __volatile__(
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|
".set push \n\t"
|
|
".set mips64 \n\t"
|
|
"dsll32 %0, %2, 0 \n\t"
|
|
"dsll32 %1, %3, 0 \n\t" /* get rid of the */
|
|
"dsrl32 %1, %1, 0 \n\t" /* sign extend */
|
|
"or %0, %0, %1 \n\t"
|
|
"lw %1, 4(%0) \n\t"
|
|
"lw %0, 0(%0) \n\t"
|
|
".set pop \n"
|
|
: "=&r"(valh), "=&r"(vall)
|
|
: "r"(addrh), "r"(addrl));
|
|
|
|
return (((uint64_t)valh << 32) | vall);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* XXX: Not really needed in n32 or n64, retain for now
|
|
*/
|
|
#if defined(__mips_n64) || defined(__mips_n32)
|
|
static __inline uint32_t
|
|
xlr_enable_kx(void)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static __inline void
|
|
xlr_restore_kx(uint32_t sr)
|
|
{
|
|
}
|
|
|
|
#else /* !defined(__mips_n64) && !defined(__mips_n32) */
|
|
/*
|
|
* o32 compilation, we will disable interrupts and enable
|
|
* the KX bit so that we can use XKPHYS to access any 40bit
|
|
* physical address
|
|
*/
|
|
static __inline uint32_t
|
|
xlr_enable_kx(void)
|
|
{
|
|
uint32_t sr = mips_rd_status();
|
|
|
|
mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
|
|
return (sr);
|
|
}
|
|
|
|
static __inline void
|
|
xlr_restore_kx(uint32_t sr)
|
|
{
|
|
|
|
mips_wr_status(sr);
|
|
}
|
|
#endif /* defined(__mips_n64) || defined(__mips_n32) */
|
|
|
|
/*
|
|
* XLR/XLS processors have maximum 8 cores, and maximum 4 threads
|
|
* per core
|
|
*/
|
|
#define XLR_MAX_CORES 8
|
|
#define XLR_NTHREADS 4
|
|
|
|
/*
|
|
* FreeBSD can be started with few threads and cores turned off,
|
|
* so have a hardware thread id to FreeBSD cpuid mapping.
|
|
*/
|
|
extern int xlr_ncores;
|
|
extern int xlr_threads_per_core;
|
|
extern uint32_t xlr_hw_thread_mask;
|
|
extern int xlr_cpuid_to_hwtid[];
|
|
extern int xlr_hwtid_to_cpuid[];
|
|
|
|
#endif
|