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aic7xxx_pci.c: When performing our register test, be careful to avoid resetting the chip when pausing the controller. The test reads the HCNTRL register and then writes it back with the PAUSE bit explicitly set. If the last write to the controller before our probe is to reset it, the CHIPRST bit will still be set, so we must mask it off before the PAUSE operation. On some chip versions, we cannot access registers for a few 100us after a reset, so this inadvertant reset was causing PCI errors to occur on the read to check for paused status. Submitted by: gibbs |
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.. | ||
aicasm | ||
ahc_eisa.c | ||
ahc_pci.c | ||
ahd_pci.c | ||
aic7xxx_93cx6.c | ||
aic7xxx_93cx6.h | ||
aic7xxx_inline.h | ||
aic7xxx_osm.c | ||
aic7xxx_osm.h | ||
aic7xxx_pci.c | ||
aic7xxx.c | ||
aic7xxx.h | ||
aic7xxx.reg | ||
aic7xxx.seq | ||
aic79xx_inline.h | ||
aic79xx_osm.c | ||
aic79xx_osm.h | ||
aic79xx_pci.c | ||
aic79xx.c | ||
aic79xx.h | ||
aic79xx.reg | ||
aic79xx.seq | ||
aic7770.c |