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112 lines
4.5 KiB
C
112 lines
4.5 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* modified for PC9801 by M.Ishii
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* Kyoto University Microcomputer Club (KMC)
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*
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* modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
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*/
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/* i8251 mode register */
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#define MOD8251_5BITS 0x00
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#define MOD8251_6BITS 0x04
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#define MOD8251_7BITS 0x08
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#define MOD8251_8BITS 0x0c
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#define MOD8251_PENAB 0x10 /* parity enable */
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#define MOD8251_PEVEN 0x20 /* parity even */
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#define MOD8251_STOP1 0x40 /* 1 stop bit */
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#define MOD8251_STOP15 0x80 /* 1.5 stop bit */
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#define MOD8251_STOP2 0xc0 /* 2 stop bit */
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#define MOD8251_CLKx1 0x01 /* x1 */
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#define MOD8251_CLKx16 0x02 /* x16 */
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#define MOD8251_CLKx64 0x03 /* x64 */
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/* i8251 command register */
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#define CMD8251_TxEN 0x01 /* transmit enable */
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#define CMD8251_DTR 0x02 /* assert DTR */
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#define CMD8251_RxEN 0x04 /* receive enable */
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#define CMD8251_SBRK 0x08 /* send break */
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#define CMD8251_ER 0x10 /* error reset */
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#define CMD8251_RTS 0x20 /* assert RTS */
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#define CMD8251_RESET 0x40 /* internal reset */
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#define CMD8251_EH 0x80 /* enter hunt mode */
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/* i8251 status register */
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#define STS8251_TxRDY 0x01 /* transmit READY */
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#define STS8251_RxRDY 0x02 /* data exists in receive buffer */
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#define STS8251_TxEMP 0x04 /* transmit buffer EMPTY */
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#define STS8251_PE 0x08 /* perity error */
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#define STS8251_OE 0x10 /* overrun error */
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#define STS8251_FE 0x20 /* framing error */
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#define STS8251_BI 0x40 /* break detect */
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#define STS8251_DSR 0x80 /* DSR is asserted */
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/* i8251F line status register */
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#define FLSR_TxEMP 0x01 /* transmit buffer EMPTY */
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#define FLSR_TxRDY 0x02 /* transmit READY */
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#define FLSR_RxRDY 0x04 /* data exists in receive buffer */
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#define FLSR_OE 0x10 /* overrun error */
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#define FLSR_PE 0x20 /* perity error */
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#define FLSR_BI 0x80 /* break detect */
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/* i8251F modem status register */
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#define MSR_DCD 0x80 /* Current Data Carrier Detect */
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#define MSR_RI 0x40 /* Current Ring Indicator */
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#define MSR_DSR 0x20 /* Current Data Set Ready */
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#define MSR_CTS 0x10 /* Current Clear to Send */
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#define MSR_DDCD 0x08 /* DCD has changed state */
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#define MSR_TERI 0x04 /* RI has toggled low to high */
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#define MSR_DDSR 0x02 /* DSR has changed state */
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#define MSR_DCTS 0x01 /* CTS has changed state */
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/* i8251F interrupt identification register */
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#define IIR_FIFO_CK1 0x40
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#define IIR_FIFO_CK2 0x20
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#define IIR_IMASK 0x0f
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#define IIR_RXTOUT 0x0c /* Receiver timeout */
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#define IIR_RLS 0x06 /* Line status change */
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#define IIR_RXRDY 0x04 /* Receiver ready */
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#define IIR_TXRDY 0x02 /* Transmitter ready */
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#define IIR_NOPEND 0x01 /* Transmitter ready */
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#define IIR_MLSC 0x00 /* Modem status */
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/* i8251F fifo control register */
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#define FIFO_ENABLE 0x01 /* Turn the FIFO on */
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#define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
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#define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
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#define FIFO_LSR_EN 0x08
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#define FIFO_MSR_EN 0x10
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#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
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#define FIFO_TRIGGER_4 0x40 /* ibid 4 */
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#define FIFO_TRIGGER_8 0x80 /* ibid 8 */
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#define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
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