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New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
254 lines
6.5 KiB
Groff
254 lines
6.5 KiB
Groff
.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 24, 2012
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.Dt PMC.OCTEON 3
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.Os
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.Sh NAME
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.Nm pmc.octeon
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.Nd measurement events for
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.Tn Octeon
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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There are two counters per core supported by the hardware and each is 64 bits
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wide.
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.Ss Event Specifiers (Programmable PMCs)
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MIPS programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li CLK
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.Pq Event 1
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Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks)
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.It Li ISSUE
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.Pq Event 2
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Instructions issued but not retired
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.It Li RET
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.Pq Event 3
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Instructions retired
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.It Li NISSUE
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.Pq Event 4
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Cycles no issue
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.It Li SISSUE
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.Pq Event 5
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Cycles single issue
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.It Li DISSUE
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.Pq Event 6
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Cycles dual issue
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.It Li IFI
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.Pq Event 7
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Cycle ifetch issued (but not necessarily commit to pp_mem)
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.It Li BR
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.Pq Event 8
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Branches retired
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.It Li BRMIS
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.Pq Event 9
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Branch mispredicts
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.It Li J
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.Pq Event 10
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Jumps retired
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.It Li JMIS
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.Pq Event 11
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Jumps mispredicted
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.It Li REPLAY
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.Pq Event 12
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Mem Replays
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.It Li IUNA
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.Pq Event 13
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Cycles idle due to unaligned_replays
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.It Li TRAP
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.Pq Event 14
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trap_6a signal
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.It Li UULOAD
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.Pq Event 16
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Unexpected unaligned loads (REPUN=1)
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.It Li UUSTORE
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.Pq Event 17
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Unexpected unaligned store (REPUN=1)
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.It Li ULOAD
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.Pq Event 18
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Unaligned loads (REPUN=1 or USEUN=1)
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.It Li USTORE
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.Pq Event 19
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Unaligned store (REPUN=1 or USEUN=1)
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.It Li EC
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.Pq Event 20
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Exec clocks(must set CvmCtl[DISCE] for accurate timing)
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.It Li MC
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.Pq Event 21
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Mul clocks(must set CvmCtl[DISCE] for accurate timing)
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.It Li CC
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.Pq Event 22
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Crypto clocks(must set CvmCtl[DISCE] for accurate timing)
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.It Li CSRC
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.Pq Event 23
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Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing)
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.It Li CFETCH
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.Pq Event 24
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Icache committed fetches (demand+prefetch)
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.It Li CPREF
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.Pq Event 25
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Icache committed prefetches
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.It Li ICA
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.Pq Event 26
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Icache aliases
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.It Li II
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.Pq Event 27
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Icache invalidates
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.It Li IP
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.Pq Event 28
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Icache parity error
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.It Li CIMISS
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.Pq Event 29
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Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing)
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.It Li WBUF
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.Pq Event 32
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Number of write buffer entries created
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.It Li WDAT
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.Pq Event 33
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Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li WBUFLD
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.Pq Event 34
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Number of write buffer entries forced out by loads
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.It Li WBUFFL
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.Pq Event 35
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Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
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.It Li WBUFTR
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.Pq Event 36
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Number of stores that found no available write buffer entries
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.It Li BADD
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.Pq Event 37
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Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li BADDL2
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.Pq Event 38
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Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li BFILL
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.Pq Event 39
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Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li DDIDS
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.Pq Event 40
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Number of Dstream DIDs created
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.It Li IDIDS
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.Pq Event 41
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Number of Istream DIDs created
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.It Li DIDNA
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.Pq Event 42
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Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
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.It Li LDS
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.Pq Event 43
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Number of load issues
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.It Li LMLDS
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.Pq Event 44
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Number of local memory load
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.It Li IOLDS
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.Pq Event 45
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Number of I/O load issues
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.It Li DMLDS
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.Pq Event 46
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Number of loads that were not prefetches and missed in the cache
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.It Li STS
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.Pq Event 48
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Number of store issues
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.It Li LMSTS
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.Pq Event 49
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Number of local memory store issues
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.It Li IOSTS
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.Pq Event 50
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Number of I/O store issues
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.It Li IOBDMA
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.Pq Event 51
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Number of IOBDMAs
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.It Li DTLB
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.Pq Event 53
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Number of dstream TLB refill, invalid, or modified exceptions
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.It Li DTLBAD
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.Pq Event 54
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Number of dstream TLB address errors
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.It Li ITLB
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.Pq Event 55
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Number of istream TLB refill, invalid, or address error exceptions
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.It Li SYNC
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.Pq Event 56
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Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li SYNCIOB
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.Pq Event 57
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Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
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.It Li SYNCW
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.Pq Event 58
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Number of SYNCWs
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.It Li ERETMIS
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.Pq Event 64
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D/eret mispredicts (CN63XX specific)
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.It Li LIKMIS
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.Pq Event 65
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Branch likely mispredicts (CN63XX specific)
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.It Li HAZTR
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.Pq Event 66
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Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific)
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.El
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.Ss Event Name Aliases
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
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.It Em Alias Ta Em Event
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.It Li instructions Ta Li RET
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.It Li branches Ta Li BR
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.It Li branch-mispredicts Ta Li BS
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.atom 3 ,
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.Xr pmc.core 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.mips24k 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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.Sh AUTHORS
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The
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.Lb libpmc
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library was written by
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.An "Joseph Koshy"
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.Aq jkoshy@FreeBSD.org .
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MIPS support was added by
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.An "George Neville-Neil"
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.Aq gnn@FreeBSD.org .
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