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<META NAME="GENERATOR" CONTENT="Mozilla/4.01 [en] (Win95; I) [Netscape]">
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<TITLE>Arcron MSF Receiver
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</TITLE>
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<BODY>
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<H3>
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Arcron MSF Receiver</H3>
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<HR>
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<H4>
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Synopsis</H4>
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Address: 127.127.27.<I>u</I>
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<BR>Reference ID: <TT>MSFa</TT>
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<BR>Driver ID: <TT>MSF_ARCRON</TT>
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<BR>Serial Port: <TT>/dev/arc<I>u</I></TT>; 300 baud, 8-bits, 2-stop, no
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parity
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<BR>Features: <TT>tty_clk</TT>
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<H4>
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Description</H4>
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This driver supports the Arcron MSF receiver, and would probably also support
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the DCF77 variant of the same clock. The clock reports its ID as ``<TT>MSFa</TT>''
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to indicate MSF as a source and the use of the ARCRON driver.
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<P>This documentation describes version V1.1 (1997/06/23) of the source
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and has been tested (amongst others) against ntpd3-5.90 on Solaris-1 (SunOS
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4.1.3_U1 on an SS1 serving as a router and firewall) and against ntpd3-5.90
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on Solaris-2.5 (on a SS1+ and TurboSPARC 170MHz). This code will probably
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work, and show increased stability, reduced jitter and more efficiency
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(fewer context switches) with the <TT>tty_clk</TT> discipline/STREAMS module
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installed, but this has not been tested. For a to-do list see the comments
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at the start of the code.
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<P>This code has been significantly slimmed down since the V1.0 version,
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roughly halving the memory footprint of its code and data.
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<P>This driver is designed to allow the unit to run from batteries as designed,
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for something approaching the 2.5 years expected in the usual stand-alone
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mode, but no battery-life measurements have been taken.
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<P>Much of this code is originally from the other refclock driver files
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with thanks. The code was originally made to work with the clock by <A HREF="mailto:derek@toybox.demon.co.uk">Derek
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Mulcahy</A>, with modifications by <A HREF="mailto:d@hd.org">Damon Hart-Davis</A>.
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Thanks also to <A HREF="mailto:lyndond@sentinet.co.uk">Lyndon David</A>
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for some of the specifications of the clock.
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<P>There is support for a Tcl/Tk monitor written by Derek Mulcahy that
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examines the output stats; see the <A HREF="http://www2.exnet.com/NTP/ARC/ARC.htm">ARC
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Rugby MSF Receiver</A> page for more details and the code.
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<P>Look at the notes at the start of the code for further information;
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some of the more important details follow.
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<P>The driver interrogates the clock at each poll (ie every 64s by default)
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for a timestamp. The clock responds at the start of the next second (with
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the start bit of the first byte being on-time). The time is in `local'
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format, including the daylight savings adjustment when it is in effect.
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The driver code converts the time back to UTC.
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<P>The clock claims to be accurate to within about 20ms of the MSF-broadcast
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time, and given the low data transmission speed from clock to host, and
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the fact that the clock is not in continuous sync with MSF, it seems sensible
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to set the `precision' of this clock to -5 or -4, -4 being used in this
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code, which builds in a reported dispersion of over 63ms (ie says ``This
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clock is not very good.''). You can improve the reported precision to -4
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(and thus reduce the base dispersion to about 31ms) by setting the fudge
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<TT>flag3</TT> to <TT>1</TT>.
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<P>Even a busy and slow IP link can yield lower dispersions than this from
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polls of primary time servers on the Internet, which reinforces the idea
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that this clock should be used as a backup in case of problems with such
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an IP link, or in the unfortunate event of failure of more accurate sources
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such as GPS.
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<P>By default this clock reports itself to be at stratum 2 rather than
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the usual stratum 0 for a refclock, because it is not really suited to
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be used as other than a backup source. The stratum reported can be changed
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with the <TT>fudge</TT> directive to be whatever you like. After careful
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monitoring of your clock, and appropriate choice of the <TT>time1</TT>
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fudge factor to remove systematic errors in the clock's reported time,
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you might fudge the clock to stratum 1 to allow a stratum-2 secondary server
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to sync to it.
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<P>The driver code arranges to resync the clock to MSF at intervals of
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a little less than an hour (deliberately avoiding the same time each hour
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to avoid any systematic problems with the signal or host). Whilst resyncing,
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the driver supplements the normal polls for time from the clock with polls
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for the reception signal quality reported by the clock. If the signal quality
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is too low (0--2 out of a range of 0--5), we chose not to trust the clock
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until the next resync (which we bring forward by about half an hour). If
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we don't catch the resync, and so don't know the signal quality, we do
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trust the clock (because this would generally be when the signal is very
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good and a resync happens quickly), but we still bring the next resync
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forward and reduce the reported precision (and thus increase reported dispersion).
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<P>If we force resyncs to MSF too often we will needlessly exhaust the
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batteries the unit runs from. During clock resync this driver tries to
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take enough time samples to avoid <TT>ntpd</TT> losing sync in case this
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clock is the current peer. By default the clock would only resync to MSF
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about once per day, which would almost certainly not be acceptable for
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NTP purposes.
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<P>The driver does not force an immediate resync of the clock to MSF when
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it starts up to avoid excessive battery drain in case <TT>ntpd</TT> is
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going to be repeatedly restarted for any reason, and also to allow enough
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samples of the clock to be taken for <TT>ntpd</TT> to sync immediately
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to this clock (and not remain unsynchronised or to sync briefly to another
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configured peer, only to hop back in a few poll times, causing unnecessary
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disturbance). This behaviour should not cause problems because the driver
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will not accept the timestamps from the clock if the status flag delivered
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with the time code indicates that the last resync attempt was unsuccessful,
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so the initial timestamps will be close to reality, even if with up to
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a day's clock drift in the worst case (the clock by default resyncs to
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MSF once per day).
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<P>The clock has a peculiar RS232 arrangement where the transmit lines
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are powered from the receive lines, presumably to minimise battery drain.
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This arrangement has two consequences:
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<UL>
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<LI>
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Your RS232 interface must drive both +ve and -ve</LI>
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<LI>
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You must (in theory) wait for an echo and a further 10ms between characters</LI>
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</UL>
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This driver, running on standard Sun hardware, seems to work fine; note
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the use of the <TT>send_slow()</TT> routine to queue up command characters
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to be sent once every two seconds.
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<P>Three commands are sent to the clock by this driver. Each command consists
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of a single letter (of which only the bottom four bits are significant),
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followed by a CR (ASCII 13). Each character sent to the clock should be
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followed by a delay to allow the unit to echo the character, and then by
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a further 10ms. Following the echo of the command string, there may be
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a response (ie in the cae of the <TT>g</TT> and <TT>o</TT> commands below),
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which in the case of the <TT>o</TT> command may be delayed by up to 1 second
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so as the start bit of the first byte of the response can arrive on time.
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The commands and their responses are:
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<DL>
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<DT>
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<TT>g</TT> CR</DT>
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<DD>
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Request for signal quality. Answer only valid during (late part of) resync
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to MSF signal. The response consists of two characters as follows:</DD>
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<OL>
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<DL compact>
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<DT>
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bit 7</DT>
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<DD>
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parity</DD>
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<DT>
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bit 6</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 5</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 4</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 3</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 2</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 1</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 0</DT>
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<DD>
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= 0 if no reception attempt at the moment, = 1 if reception attempt (ie
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resync) in progress</DD>
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</DL>
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<DL compact>
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<DT>
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bit 7</DT>
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<DD>
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parity</DD>
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<DT>
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bit 6</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 5</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 4</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 3</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 2--0</DT>
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<DD>
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reception signal quality in the range 0--5 (very poor to very good); if
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in the range 0--2 no successful reception is to be expected. The reported
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value drops to zero when not resyncing, ie when first returned byte is
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not `3'.</DD>
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</DL>
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</OL>
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<DT>
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<TT>h</TT> CR</DT>
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<DD>
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Request to resync to MSF. Can take up from about 30s to 360s. Drains batteries
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so should not be used excessively. After this the clock time and date should
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be correct and the phase within 20ms of time as transmitted from Rugby
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MSF (remember to allow for propagation time). By default the clock resyncs
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once per day shortly after 2am (presumably to catch transitions to/from
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daylight saving time quickly). With this driver code we resync at least
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once per hour to minimise clock wander.</DD>
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<DT>
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<TT>o</TT> CR</DT>
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<DD>
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Request timestamp. Start bit of first byte of response is on-time, so may
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be delayed up to 1 second. Note that when the BST mode is in effect the
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time is GMT/UTC +0100, ie an hour ahead of UTC to reflect local time in
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the UK. The response data is as follows:</DD>
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<OL>
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<LI>
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hours tens (hours range from 00 to 23)</LI>
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<LI>
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hours units</LI>
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<LI>
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minutes tens (minutes range from 00 to 59)</LI>
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<LI>
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minutes units</LI>
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<LI>
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seconds tens (seconds presumed to range from 00 to 60 to allow for leap
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second)</LI>
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<LI>
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seconds units</LI>
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<LI>
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day of week 1 (Monday) to 7 (Sunday)</LI>
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<LI>
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day of month tens (day ranges from 01 to 31)</LI>
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<LI>
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day of month units</LI>
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<LI>
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month tens (months range from 01 to 12)</LI>
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<LI>
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month units</LI>
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<LI>
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year tens (years range from 00 to 99)</LI>
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<LI>
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year units</LI>
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<LI>
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BST/UTC status</LI>
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<DL compact>
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<DT>
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bit 7</DT>
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<DD>
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parity</DD>
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<DT>
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bit 6</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 5</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 4</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 3</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 2</DT>
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<DD>
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= 1 if UTC is in effect (reverse of bit 1)</DD>
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<DT>
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bit 1</DT>
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<DD>
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= 1 if BST is in effect (reverse of bit 2)</DD>
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<DT>
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bit 0</DT>
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<DD>
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= 1 if BST/UTC change pending</DD>
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</DL>
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<LI>
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clock status</LI>
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<DL compact>
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<DT>
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bit 7</DT>
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<DD>
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parity</DD>
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<DT>
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bit 6</DT>
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<DD>
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always 0</DD>
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<DT>
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bit 5</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 4</DT>
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<DD>
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always 1</DD>
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<DT>
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bit 3</DT>
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<DD>
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= 1 if low battery is detected</DD>
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<DT>
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bit 2</DT>
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<DD>
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= 1 if last resync failed (though officially undefined for the MSF clock)</DD>
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<DT>
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bit 1</DT>
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<DD>
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= 1 if at least one reception attempt since 0230 for the MSF clock was
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successful (0300 for the DCF77 clock)</DD>
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<DT>
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bit 0</DT>
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<DD>
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= 1 if the clock has valid time---reset to zero when clock is reset (eg
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at power-up), and set to 1 after first successful resync attempt.</DD>
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</DL>
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</OL>
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The driver only accepts time from the clock if the bottom three bits of
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the status byte are <TT>011</TT>. The leap-year logic for computing day-in-year
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is only valid until 2099, and the clock will ignore stamps from the clock
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that claim BST is in effect in the first hour of each year. If the UK parliament
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decides to move us to +0100/+0200 time as opposed to the current +0000/+0100
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time, it is not clear what effect that will have on the time broadcast
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by MSF, and therefore on this driver's usefulness.</DL>
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A typical <TT>ntp.conf</TT> configuration file for this driver might be:
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<PRE># hostname(n) means we expect (n) to be the stratum at which hostname runs.
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#------------------------------------------------------------------------------
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# SYNCHRONISATION PARTNERS
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# ========================
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# Our betters...
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server 127.127.27.0 # ARCRON MSF radio clock(1).
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# Fudge stratum and other features as required.
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# ADJUST time1 VALUE FOR YOUR HOST, CLOCK AND LOCATION!
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fudge 127.127.27.0 stratum 1 time1 0.016 flag3 1 flag4 1
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peer 11.22.33.9 # tick(1--2).
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peer 11.22.33.4 # tock(3), boot/NFS server.
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# This shouldn't get swept away unless left untouched for a long time.
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driftfile /var/tmp/ntp.drift
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#------------------------------------------------------------------------------
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# RESTRICTIONS
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# ============
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# By default, don't trust and don't allow modifications. Ignore in fact.
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restrict default ignore notrust nomodify
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# Allow others in our subnet to check us out...
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restrict 11.22.33.0 mask 255.255.255.0 nomodify notrust
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# Trust our peers for time. Don't trust others in case they are insane.
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restrict 127.127.27.0 nomodify
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restrict 11.22.33.4 nomodify
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restrict 11.22.33.9 nomodify
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# Allow anything from the local host.
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restrict 127.0.0.1</PRE>
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There are a few <TT>#define</TT>s in the code that you might wish to play
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with:
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<DL>
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<DT>
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<TT>ARCRON_KEEN</TT></DT>
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<DD>
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With this defined, the code is relatively trusting of the clock, and assumes
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that you will have the clock as one of a few time sources, so will bend
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over backwards to use the time from the clock when available and avoid
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<TT>ntpd</TT> dropping sync from the clock where possible. You may wish
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to undefine this, especially if you have better sources of time or your
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reception is ropey. However, there are many checks built in even with this
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flag defined.</DD>
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<DT>
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<TT>ARCRON_OWN_FILTER</TT></DT>
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<DD>
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When defined, the code uses its own median-filter code rather than that
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available in <TT>ntp_refclock.c</TT> since the latter seems to have a minor
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bug, at least in version 3-5.90. If this bug goes away this flag should
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be turned off to avoid duplication of code. (The bug, if that's what it
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is, causes the last raw offset to be used rather than the median offset.)</DD>
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<P>Without this defined (and without <TT>ARCRON_MULTIPLE_SAMPLES</TT> below)
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a typical set of offsets reported and used to drive the clock-filter algorithm
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is (oldest last):
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<PRE>filtoffset= -4.32 -34.82 -0.78 0.89 2.76 4.58 -3.92 -2.17</PRE>
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Look at that spike!
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<P>With this defined a typical set of offsets is:
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<PRE>filtoffset= -7.06 -7.06 -2.91 -2.91 -2.91 -1.27 -9.54 -6.70</PRE>
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with the repeated values being some evidence of outlyers being discarded.
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<DT>
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<TT>ARCRON_MULTIPLE_SAMPLES</TT></DT>
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<DD>
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When is defined, we regard each character in the returned timecode as at
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a known delay from the start of the second, and use the smallest (most
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negative) offset implied by any such character, ie with the smallest kernel-induced
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display, and use that. This helps to reduce jitter and spikes.</DD>
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<DT>
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<TT>ARCRON_LEAPSECOND_KEEN</TT></DT>
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<DD>
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When is defined, we try to do a resync to MSF as soon as possible in the
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first hour of the morning of the first day of the first and seventh months,
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ie just after a leap-second insertion or deletion would happen if it is
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going to. This should help compensate for the fact that this clock does
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not continuously sample MSF, which compounds the fact that MSF itself gives
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no warning of an impending leap-second event. This code did not seem functional
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at the leap-second insertion of 30th June 1997 so is by default disabled.</DD>
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<DT>
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<TT>PRECISION</TT></DT>
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<DD>
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Currently set to <TT>-4</TT>, but you may wish to set it to <TT>-5</TT>
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if you are more conservative, or to <TT>-6</TT> if you have particularly
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good experience with the clock and you live on the edge. Note that the
|
|
<TT>flag3</TT> fudge value will improve the reported dispersion one notch
|
|
if clock signal quality is known good. So maybe just leave this alone.
|
|
B^)</DD>
|
|
|
|
<DT>
|
|
<TT>NSAMPLES</TT></DT>
|
|
|
|
<DD>
|
|
Should be at least 3 to help smooth out sampling jitters. Can be more,
|
|
but if made too long can make <TT>ntpd</TT> overshoot on clock corrections
|
|
and can hold onto bad samples longer than you would like. With this set
|
|
to 4 and <TT>NKEEP</TT> set to 3 this allows the occasional bad sample
|
|
(in my experience less than 1 value in 10) to be dropped. (Note that there
|
|
seems to be some sort of `beat' effect in the offset with a periodicity
|
|
of about 7 samples as of this writing (1997/05/11) still under investigation;
|
|
a filter of approximately this length should be able to almost completely
|
|
suppress this effect.) Note that if the fudge-factor <TT>flag3</TT> is
|
|
set to 1, a larger <TT>NSAMPLES</TT> is used.</DD>
|
|
</DL>
|
|
|
|
<H4>
|
|
Monitor Data</H4>
|
|
Each timecode is written to the <TT>clockstats</TT> file with a signal
|
|
quality value appended (`0'--`5' as reported by the clock, or `6' for unknown).
|
|
|
|
<P>Each resync and result (plus gaining or losing MSF sync) is logged to
|
|
the system log at level <TT>LOG_NOTICE</TT>; note that each resync drains
|
|
the unit's batteries, so the syslog entry seems justified.
|
|
|
|
<P>Syslog entries are of the form:
|
|
<PRE>May 10 10:15:24 oolong ntpd[615]: ARCRON: unit 0: sending resync command
|
|
May 10 10:17:32 oolong ntpd[615]: ARCRON: sync finished, signal quality 5: OK, will use clock
|
|
May 10 11:13:01 oolong ntpd[615]: ARCRON: unit 0: sending resync command
|
|
May 10 11:14:06 oolong ntpd[615]: ARCRON: sync finished, signal quality -1: UNKNOWN, will use clock anyway
|
|
May 10 11:41:49 oolong ntpd[615]: ARCRON: unit 0: sending resync command
|
|
May 10 11:43:57 oolong ntpd[615]: ARCRON: sync finished, signal quality 5: OK, will use clock
|
|
May 10 12:39:26 oolong ntpd[615]: ARCRON: unit 0: sending resync command
|
|
May 10 12:41:34 oolong ntpd[615]: ARCRON: sync finished, signal quality 3: OK, will use clock</PRE>
|
|
|
|
<H4>
|
|
Fudge Factors</H4>
|
|
|
|
<DL>
|
|
<DT>
|
|
<TT>time1 <I>time</I></TT></DT>
|
|
|
|
<DD>
|
|
Specifies the time offset calibration factor, in seconds and fraction,
|
|
with default 0.0. On a Sun SparcStation 1 running SunOS 4.1.3_U1, with
|
|
the receiver in London, a value of 0.020 (20ms) seems to be appropriate.</DD>
|
|
|
|
<DT>
|
|
<TT>time2 <I>time</I></TT></DT>
|
|
|
|
<DD>
|
|
Not currently used by this driver.</DD>
|
|
|
|
<DT>
|
|
<TT>stratum <I>number</I></TT></DT>
|
|
|
|
<DD>
|
|
Specifies the driver stratum, in decimal from 0 to 15, with default 0.
|
|
It is suggested that the clock be fudged to stratum 1 so this it is used
|
|
a backup time source rather than a primary when more accurate sources are
|
|
available.</DD>
|
|
|
|
<DT>
|
|
<TT>refid <I>string</I></TT></DT>
|
|
|
|
<DD>
|
|
Specifies the driver reference identifier, an ASCII string from one to
|
|
four characters, with default <TT>MSFa</TT>.</DD>
|
|
|
|
<DT>
|
|
<TT>flag1 0 | 1</TT></DT>
|
|
|
|
<DD>
|
|
Not used by this driver.</DD>
|
|
|
|
<DT>
|
|
<TT>flag2 0 | 1</TT></DT>
|
|
|
|
<DD>
|
|
Not used by this driver.</DD>
|
|
|
|
<DT>
|
|
<TT>flag3 0 | 1</TT></DT>
|
|
|
|
<DD>
|
|
If set to 1, better precision is reported (and thus lower dispersion) while
|
|
clock's received signal quality is known to be good.</DD>
|
|
|
|
<DT>
|
|
<TT>flag4 0 | 1</TT></DT>
|
|
|
|
<DD>
|
|
If set to 1, a longer-than-normal (8-stage rather than 4-stage) median
|
|
filter is used, to provide some extra smoothing of clock output and reduction
|
|
in jitter, at the cost of extra clock overshoot. Probably not advisable
|
|
unless the server using this clock has other sources it can use to help
|
|
mitigate the overshoot.</DD>
|
|
</DL>
|
|
|
|
<H4>
|
|
Additional Information</H4>
|
|
<A HREF="refclock.htm">Reference Clock Drivers</A>
|
|
|
|
<P><A HREF="http://www2.exnet.com/NTP/ARC/ARC.htm">ARC Rugby MSF Receiver</A>
|
|
page
|
|
<HR>
|
|
<ADDRESS>
|
|
Damon Hart-Davis (d@hd.org)</ADDRESS>
|
|
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</BODY>
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