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fd75b91d13
(which should be a PCIE Gen 3 slot for this adapter) by looking back thru the PCI parent devices to the slot device. The fix above also corrects the bandwidth display to GT/s rather than the incorrect Gb/s Next, allow the use of ALTQ if you select the compile option IXGBE_LEGACY_TX. Allow the use of 'unsupported' optic modules by a compile option as well. Add a phy reset capability into the stop code, this is so a static configured driver will still behave properly when taken down (not being able to unload it). This revision synchronizes the shared code with Intel internal current code, and note that it now includes DCB supporting code, this was necessitated by some internal changes with the code, but it also will provide the opportunity to develop this feature in the core driver down the road. I have edited the README to get rid of some of the worse anachronisms in it as well, its by no means as robust as I might wish at this point however. Oh, I also have included some conditional stuff in the code so it will be compatible in both the 9.X and 10 environments. Performance has been a focus in recent changes and I believe this revision driver will perform very well in most workloads. MFC after: 2 weeks
587 lines
17 KiB
C
587 lines
17 KiB
C
/******************************************************************************
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Copyright (c) 2001-2013, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82599.h"
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/**
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* ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the status data for each of the Traffic Classes in use.
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*/
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s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
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struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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int tc;
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DEBUGFUNC("dcb_get_tc_stats");
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if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
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return IXGBE_ERR_PARAM;
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/* Statistics pertaining to each traffic class */
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for (tc = 0; tc < tc_count; tc++) {
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/* Transmitted Packets */
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stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
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/* Transmitted Bytes (read low first to prevent missed carry) */
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stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
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stats->qbtc[tc] +=
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(((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
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/* Received Packets */
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stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
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/* Received Bytes (read low first to prevent missed carry) */
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stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
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stats->qbrc[tc] +=
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(((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
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/* Received Dropped Packet */
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stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the CBFC status data for each of the Traffic Classes.
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*/
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s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
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struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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int tc;
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DEBUGFUNC("dcb_get_pfc_stats");
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if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
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return IXGBE_ERR_PARAM;
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for (tc = 0; tc < tc_count; tc++) {
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/* Priority XOFF Transmitted */
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stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
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/* Priority XOFF Received */
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stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Rx Packet Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa,
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u8 *map)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; WSP)
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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/*
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* map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
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* bits sets for the UPs that needs to be mappped to that TC.
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* e.g if priorities 6 and 7 are to be mapped to a TC then the
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* up_to_tc_bitmap value for that TC will be 11000000 in binary.
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*/
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reg = 0;
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for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
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reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
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reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_RTRPT4C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
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}
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/*
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* Configure Rx packet plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
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IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa)
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{
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u32 reg, max_credits;
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u8 i;
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/* Clear the per-Tx queue credits; we use per-TC instead */
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for (i = 0; i < 128; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
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}
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
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if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
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reg |= IXGBE_RTTDT2C_GSP;
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_RTTDT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
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}
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/*
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* Configure Tx descriptor plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Packet Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa,
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u8 *map)
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{
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u32 reg;
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u8 i;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; SP; arb delay)
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
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IXGBE_RTTPCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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/*
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* map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
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* bits sets for the UPs that needs to be mappped to that TC.
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* e.g if priorities 6 and 7 are to be mapped to a TC then the
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* up_to_tc_bitmap value for that TC will be 11000000 in binary.
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*/
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reg = 0;
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for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
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reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
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if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
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reg |= IXGBE_RTTPT2C_GSP;
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_RTTPT2C_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
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}
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/*
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* Configure Tx packet plane (recycle mode; SP; arb delay) and
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* enable arbiter
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*/
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reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
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(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_pfc_82599 - Configure priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @map: priority to tc assignments indexed by priority
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*
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* Configure Priority Flow Control (PFC) for each traffic class.
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*/
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
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{
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u32 i, j, fcrtl, reg;
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u8 max_tc = 0;
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/* Enable Transmit Priority Flow Control */
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IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
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/* Enable Receive Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
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reg |= IXGBE_MFLCN_DPF;
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/*
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* X540 supports per TC Rx priority flow control. So
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* clear all TCs and only enable those that should be
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* enabled.
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*/
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reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
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if (hw->mac.type == ixgbe_mac_X540)
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reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
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if (pfc_en)
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reg |= IXGBE_MFLCN_RPFCE;
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IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
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for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
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if (map[i] > max_tc)
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max_tc = map[i];
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}
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i <= max_tc; i++) {
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int enabled = 0;
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for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
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if ((map[j] == i) && (pfc_en & (1 << j))) {
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enabled = 1;
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break;
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}
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}
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if (enabled) {
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reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
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} else {
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reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
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}
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for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
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}
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/* Configure pause time (2 TCs per register) */
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reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
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for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config)
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{
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u32 reg = 0;
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u8 i = 0;
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u8 tc_count = 8;
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bool vt_mode = FALSE;
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if (dcb_config != NULL) {
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tc_count = dcb_config->num_tcs.pg_tcs;
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vt_mode = dcb_config->vt_mode;
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}
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if (!((tc_count == 8 && vt_mode == FALSE) || tc_count == 4))
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return IXGBE_ERR_PARAM;
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if (tc_count == 8 && vt_mode == FALSE) {
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/*
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* Receive Queues stats setting
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* 32 RQSMR registers, each configuring 4 queues.
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*
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* Set all 16 queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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*/
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for (i = 0; i < 32; i++) {
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reg = 0x01010101 * (i / 4);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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}
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/*
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* Transmit Queues stats setting
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* 32 TQSM registers, each controlling 4 queues.
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*
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* Set all queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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* Tx queues are allocated non-uniformly to TCs:
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* 32, 32, 16, 16, 8, 8, 8, 8.
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*/
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for (i = 0; i < 32; i++) {
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if (i < 8)
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reg = 0x00000000;
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else if (i < 16)
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reg = 0x01010101;
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else if (i < 20)
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reg = 0x02020202;
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else if (i < 24)
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reg = 0x03030303;
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else if (i < 26)
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reg = 0x04040404;
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else if (i < 28)
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reg = 0x05050505;
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else if (i < 30)
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reg = 0x06060606;
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else
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reg = 0x07070707;
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IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
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}
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} else if (tc_count == 4 && vt_mode == FALSE) {
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/*
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* Receive Queues stats setting
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* 32 RQSMR registers, each configuring 4 queues.
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*
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* Set all 16 queues of each TC to the same stat
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* with TC 'n' going to stat 'n'.
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*/
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for (i = 0; i < 32; i++) {
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if (i % 8 > 3)
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/* In 4 TC mode, odd 16-queue ranges are
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* not used.
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*/
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continue;
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reg = 0x01010101 * (i / 8);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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}
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/*
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* Transmit Queues stats setting
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* 32 TQSM registers, each controlling 4 queues.
|
|
*
|
|
* Set all queues of each TC to the same stat
|
|
* with TC 'n' going to stat 'n'.
|
|
* Tx queues are allocated non-uniformly to TCs:
|
|
* 64, 32, 16, 16.
|
|
*/
|
|
for (i = 0; i < 32; i++) {
|
|
if (i < 16)
|
|
reg = 0x00000000;
|
|
else if (i < 24)
|
|
reg = 0x01010101;
|
|
else if (i < 28)
|
|
reg = 0x02020202;
|
|
else
|
|
reg = 0x03030303;
|
|
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
|
|
}
|
|
} else if (tc_count == 4 && vt_mode == TRUE) {
|
|
/*
|
|
* Receive Queues stats setting
|
|
* 32 RQSMR registers, each configuring 4 queues.
|
|
*
|
|
* Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
|
|
* pool. Set all 32 queues of each TC across pools to the same
|
|
* stat with TC 'n' going to stat 'n'.
|
|
*/
|
|
for (i = 0; i < 32; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
|
|
/*
|
|
* Transmit Queues stats setting
|
|
* 32 TQSM registers, each controlling 4 queues.
|
|
*
|
|
* Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
|
|
* pool. Set all 32 queues of each TC across pools to the same
|
|
* stat with TC 'n' going to stat 'n'.
|
|
*/
|
|
for (i = 0; i < 32; i++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
|
|
}
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_config_82599 - Configure general DCB parameters
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure general DCB parameters.
|
|
*/
|
|
s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
|
|
struct ixgbe_dcb_config *dcb_config)
|
|
{
|
|
u32 reg;
|
|
u32 q;
|
|
|
|
/* Disable the Tx desc arbiter so that MTQC can be changed */
|
|
reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
|
|
reg |= IXGBE_RTTDCS_ARBDIS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
|
|
|
|
reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
|
|
if (dcb_config->num_tcs.pg_tcs == 8) {
|
|
/* Enable DCB for Rx with 8 TCs */
|
|
switch (reg & IXGBE_MRQC_MRQE_MASK) {
|
|
case 0:
|
|
case IXGBE_MRQC_RT4TCEN:
|
|
/* RSS disabled cases */
|
|
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
|
|
IXGBE_MRQC_RT8TCEN;
|
|
break;
|
|
case IXGBE_MRQC_RSSEN:
|
|
case IXGBE_MRQC_RTRSS4TCEN:
|
|
/* RSS enabled cases */
|
|
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
|
|
IXGBE_MRQC_RTRSS8TCEN;
|
|
break;
|
|
default:
|
|
/*
|
|
* Unsupported value, assume stale data,
|
|
* overwrite no RSS
|
|
*/
|
|
ASSERT(0);
|
|
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
|
|
IXGBE_MRQC_RT8TCEN;
|
|
}
|
|
}
|
|
if (dcb_config->num_tcs.pg_tcs == 4) {
|
|
/* We support both VT-on and VT-off with 4 TCs. */
|
|
if (dcb_config->vt_mode)
|
|
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
|
|
IXGBE_MRQC_VMDQRT4TCEN;
|
|
else
|
|
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
|
|
IXGBE_MRQC_RTRSS4TCEN;
|
|
}
|
|
IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
|
|
|
|
/* Enable DCB for Tx with 8 TCs */
|
|
if (dcb_config->num_tcs.pg_tcs == 8)
|
|
reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
|
|
else {
|
|
/* We support both VT-on and VT-off with 4 TCs. */
|
|
reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
|
|
if (dcb_config->vt_mode)
|
|
reg |= IXGBE_MTQC_VT_ENA;
|
|
}
|
|
IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
|
|
|
|
/* Disable drop for all queues */
|
|
for (q = 0; q < 128; q++)
|
|
IXGBE_WRITE_REG(hw, IXGBE_QDE,
|
|
(IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
|
|
|
|
/* Enable the Tx desc arbiter */
|
|
reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
|
|
reg &= ~IXGBE_RTTDCS_ARBDIS;
|
|
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
|
|
|
|
/* Enable Security TX Buffer IFG for DCB */
|
|
reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
|
|
reg |= IXGBE_SECTX_DCB;
|
|
IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure dcb settings and enable dcb mode.
|
|
*/
|
|
s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
|
|
u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
|
|
u8 *map)
|
|
{
|
|
|
|
ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
|
|
map);
|
|
ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
|
|
tsa);
|
|
ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
|
|
tsa, map);
|
|
|
|
return IXGBE_SUCCESS;
|
|
}
|
|
|