Alexander Motin 08c8fde007 According to SATA specification, when Serial ATA Enclosure Management Bridge ... (SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in response to hard and soft resets it should among other things return value 0x7F in Status register. The weird side is that it means DRQ bit set, which tells that reset request is not completed. It would be fine if SEMB was the only device on port. But if SEMB connected to PMP or built into it, it may block access to other devices sharing same SATA port. Make some tunings/fixes to soft-reset handling to workaround the issue: - ahci(4): request CLO on the port after soft reset to ignore DRQ bit; - siis(4): gracefully reinitialize port after soft reset timeout (hardware doesn't detect reset request completion in this case); - mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it clear DRQ bit for us. For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726 PMPs, less important. Further, if hardware permit, I hope to implement real SEMB support.		2011-05-25 13:55:49 +00:00
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mvs_if.m
mvs_pci.c
mvs_soc.c
mvs.c	According to SATA specification, when Serial ATA Enclosure Management Bridge	2011-05-25 13:55:49 +00:00
mvs.h