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c40da00ca3
unnecessary.
799 lines
18 KiB
C
799 lines
18 KiB
C
/* $NecBSD: bshw_machdep.c,v 1.8.12.6 2001/06/29 06:28:05 honda Exp $ */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/* $NetBSD$ */
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/*-
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* [NetBSD for NEC PC-98 series]
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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* NetBSD/pc98 porting staff. All rights reserved.
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*
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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* Naofumi HONDA. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#if defined(__FreeBSD__) && __FreeBSD_version > 500001
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#include <sys/bio.h>
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#endif /* __ FreeBSD__ */
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#include <sys/buf.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/errno.h>
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#include <vm/vm.h>
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#ifdef __NetBSD__
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_disk.h>
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#include <machine/dvcfg.h>
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#include <machine/physio_proc.h>
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#include <i386/Cbus/dev/scsi_low.h>
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#include <dev/ic/wd33c93reg.h>
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#include <i386/Cbus/dev/ct/ctvar.h>
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#include <i386/Cbus/dev/ct/ct_machdep.h>
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#include <i386/Cbus/dev/ct/bshwvar.h>
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#endif /* __NetBSD__ */
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#ifdef __FreeBSD__
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <compat/netbsd/dvcfg.h>
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#include <compat/netbsd/physio_proc.h>
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#include <cam/scsi/scsi_low.h>
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#include <dev/ic/wd33c93reg.h>
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#include <dev/ct/ctvar.h>
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#include <dev/ct/ct_machdep.h>
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#include <dev/ct/bshwvar.h>
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#include <vm/pmap.h>
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#endif /* __FreeBSD__ */
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#define BSHW_IO_CONTROL_FLAGS 0
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u_int bshw_io_control = BSHW_IO_CONTROL_FLAGS;
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int bshw_data_read_bytes = 4096;
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int bshw_data_write_bytes = 4096;
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/*********************************************************
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* OS dep part
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*********************************************************/
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#ifdef __NetBSD__
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#define BSHW_PAGE_SIZE NBPG
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#endif /* __NetBSD__ */
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#ifdef __FreeBSD__
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#define BSHW_PAGE_SIZE PAGE_SIZE
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typedef unsigned long vaddr_t;
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#endif /* __FreeBSD__ */
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/*********************************************************
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* GENERIC MACHDEP FUNCTIONS
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*********************************************************/
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void
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bshw_synch_setup(ct, ti)
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struct ct_softc *ct;
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struct targ_info *ti;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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struct ct_targ_info *cti = (void *) ti;
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struct bshw_softc *bs = ct->ct_hw;
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struct bshw *hw = bs->sc_hw;
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if (hw->hw_sregaddr == 0)
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return;
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ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id, cti->cti_syncreg);
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if (hw->hw_flags & BSHW_DOUBLE_DMACHAN)
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{
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ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id + 8,
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cti->cti_syncreg);
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}
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}
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void
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bshw_bus_reset(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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struct bshw_softc *bs = ct->ct_hw;
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struct bshw *hw = bs->sc_hw;
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bus_addr_t offs;
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u_int8_t regv;
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int i;
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/* open hardware busmaster mode */
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if (hw->hw_dma_init != NULL && ((*hw->hw_dma_init)(ct)) != 0)
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{
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printf("%s: change mode using external DMA (%x)\n",
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slp->sl_xname, (u_int)ct_cr_read_1(chp, 0x37));
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}
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/* clear hardware synch registers */
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offs = hw->hw_sregaddr;
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if (offs != 0)
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{
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for (i = 0; i < 8; i ++, offs ++)
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{
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ct_cr_write_1(chp, offs, 0);
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if ((hw->hw_flags & BSHW_DOUBLE_DMACHAN) != 0)
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ct_cr_write_1(chp, offs + 8, 0);
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}
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}
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/* disable interrupt & assert reset */
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regv = ct_cr_read_1(chp, wd3s_mbank);
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regv |= MBR_RST;
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regv &= ~MBR_IEN;
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ct_cr_write_1(chp, wd3s_mbank, regv);
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SCSI_LOW_DELAY(500000);
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/* reset signal off */
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regv &= ~MBR_RST;
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ct_cr_write_1(chp, wd3s_mbank, regv);
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/* interrupt enable */
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regv |= MBR_IEN;
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ct_cr_write_1(chp, wd3s_mbank, regv);
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}
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/* probe */
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int
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bshw_read_settings(chp, bs)
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struct ct_bus_access_handle *chp;
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struct bshw_softc *bs;
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{
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static int irq_tbl[] = { 3, 5, 6, 9, 12, 13 };
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bs->sc_hostid = (ct_cr_read_1(chp, wd3s_auxc) & AUXCR_HIDM);
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bs->sc_irq = irq_tbl[(ct_cr_read_1(chp, wd3s_auxc) >> 3) & 7];
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bs->sc_drq = ct_cmdp_read_1(chp) & 3;
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return 0;
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}
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/*********************************************************
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* DMA PIO TRANSFER (SMIT)
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*********************************************************/
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#define LC_SMIT_TIMEOUT 2 /* 2 sec: timeout for a fifo status ready */
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#define LC_SMIT_OFFSET 0x1000
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#define LC_FSZ DEV_BSIZE
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#define LC_SFSZ 0x0c
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#define LC_REST (LC_FSZ - LC_SFSZ)
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#define BSHW_LC_FSET 0x36
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#define BSHW_LC_FCTRL 0x44
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#define FCTRL_EN 0x01
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#define FCTRL_WRITE 0x02
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#define SF_ABORT 0x08
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#define SF_RDY 0x10
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static __inline void bshw_lc_smit_start(struct ct_softc *, int, u_int);
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static __inline void bshw_lc_smit_stop(struct ct_softc *);
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static int bshw_lc_smit_fstat(struct ct_softc *, int, int);
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static __inline void
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bshw_lc_smit_stop(ct)
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struct ct_softc *ct;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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ct_cr_write_1(chp, BSHW_LC_FCTRL, 0);
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ct_cmdp_write_1(chp, CMDP_DMER);
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}
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static __inline void
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bshw_lc_smit_start(ct, count, direction)
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struct ct_softc *ct;
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int count;
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u_int direction;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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u_int8_t pval, val;
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val = ct_cr_read_1(chp, BSHW_LC_FSET);
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cthw_set_count(chp, count);
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pval = FCTRL_EN;
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if (direction == SCSI_LOW_WRITE)
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pval |= (val & 0xe0) | FCTRL_WRITE;
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ct_cr_write_1(chp, BSHW_LC_FCTRL, pval);
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ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
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}
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static int
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bshw_lc_smit_fstat(ct, wc, read)
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struct ct_softc *ct;
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int wc, read;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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u_int8_t stat;
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while (wc -- > 0)
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{
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chp->ch_bus_weight(chp);
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stat = ct_cmdp_read_1(chp);
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if (read == SCSI_LOW_READ)
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{
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if ((stat & SF_RDY) != 0)
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return 0;
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if ((stat & SF_ABORT) != 0)
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return EIO;
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}
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else
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{
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if ((stat & SF_ABORT) != 0)
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return EIO;
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if ((stat & SF_RDY) != 0)
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return 0;
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}
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}
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printf("%s: SMIT fifo status timeout\n", ct->sc_sclow.sl_xname);
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return EIO;
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}
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void
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bshw_smit_xfer_stop(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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struct bshw_softc *bs = ct->ct_hw;
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struct targ_info *ti;
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struct sc_p *sp = &slp->sl_scp;
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u_int count;
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bshw_lc_smit_stop(ct);
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ti = slp->sl_Tnexus;
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if (ti == NULL)
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return;
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if (ti->ti_phase == PH_DATA)
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{
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count = cthw_get_count(&ct->sc_ch);
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if (count < bs->sc_sdatalen)
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{
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if (sp->scp_direction == SCSI_LOW_READ &&
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count != bs->sc_edatalen)
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goto bad;
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count = bs->sc_sdatalen - count;
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if (count > (u_int) sp->scp_datalen)
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goto bad;
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sp->scp_data += count;
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sp->scp_datalen -= count;
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}
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else if (count > bs->sc_sdatalen)
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{
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bad:
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printf("%s: smit_xfer_end: cnt error\n", slp->sl_xname);
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slp->sl_error |= PDMAERR;
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}
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scsi_low_data_finish(slp);
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}
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else
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{
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printf("%s: smit_xfer_end: phase miss\n", slp->sl_xname);
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slp->sl_error |= PDMAERR;
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}
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}
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int
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bshw_smit_xfer_start(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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struct bshw_softc *bs = ct->ct_hw;
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struct sc_p *sp = &slp->sl_scp;
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struct targ_info *ti = slp->sl_Tnexus;
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struct ct_targ_info *cti = (void *) ti;
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u_int datalen, count, io_control;
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int wc;
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u_int8_t *data;
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io_control = bs->sc_io_control | bshw_io_control;
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if ((io_control & BSHW_SMIT_BLOCK) != 0)
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return EINVAL;
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if ((slp->sl_scp.scp_datalen % DEV_BSIZE) != 0)
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return EINVAL;
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datalen = sp->scp_datalen;
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if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
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{
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if ((io_control & BSHW_READ_INTERRUPT_DRIVEN) != 0 &&
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datalen > bshw_data_read_bytes)
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datalen = bshw_data_read_bytes;
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}
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else
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{
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if ((io_control & BSHW_WRITE_INTERRUPT_DRIVEN) != 0 &&
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datalen > bshw_data_write_bytes)
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datalen = bshw_data_write_bytes;
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}
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bs->sc_sdatalen = datalen;
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data = sp->scp_data;
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wc = LC_SMIT_TIMEOUT * 1024 * 1024;
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ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
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bshw_lc_smit_start(ct, datalen, sp->scp_direction);
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if (sp->scp_direction == SCSI_LOW_READ)
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{
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do
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{
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if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_READ))
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break;
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count = (datalen > LC_FSZ ? LC_FSZ : datalen);
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bus_space_read_region_4(chp->ch_memt, chp->ch_memh,
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LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
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data += count;
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datalen -= count;
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}
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while (datalen > 0);
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bs->sc_edatalen = datalen;
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}
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else
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{
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do
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{
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if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
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break;
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if (cti->cti_syncreg == 0)
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{
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/* XXX:
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* If async transfer, reconfirm a scsi phase
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* again. Unless C bus might hang up.
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*/
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if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
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break;
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}
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count = (datalen > LC_SFSZ ? LC_SFSZ : datalen);
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bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
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LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
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data += count;
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datalen -= count;
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if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
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break;
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count = (datalen > LC_REST ? LC_REST : datalen);
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bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
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LC_SMIT_OFFSET + LC_SFSZ,
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(u_int32_t *) data, count >> 2);
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data += count;
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datalen -= count;
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}
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while (datalen > 0);
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}
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return 0;
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}
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|
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/*********************************************************
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* DMA TRANSFER (BS)
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*********************************************************/
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static __inline void bshw_dma_write_1 \
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(struct ct_bus_access_handle *, bus_addr_t, u_int8_t);
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static void bshw_dmastart(struct ct_softc *);
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static void bshw_dmadone(struct ct_softc *);
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int
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bshw_dma_xfer_start(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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struct sc_p *sp = &slp->sl_scp;
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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struct bshw_softc *bs = ct->ct_hw;
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vaddr_t va, endva, phys, nphys;
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u_int io_control;
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io_control = bs->sc_io_control | bshw_io_control;
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if ((io_control & BSHW_DMA_BLOCK) != 0 && sp->scp_datalen < 256)
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return EINVAL;
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ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
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phys = vtophys((vaddr_t) sp->scp_data);
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if (phys >= bs->sc_minphys)
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{
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/* setup segaddr */
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bs->sc_segaddr = bs->sc_bounce_phys;
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/* setup seglen */
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bs->sc_seglen = sp->scp_datalen;
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if (bs->sc_seglen > bs->sc_bounce_size)
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bs->sc_seglen = bs->sc_bounce_size;
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/* setup bufp */
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bs->sc_bufp = bs->sc_bounce_addr;
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if (sp->scp_direction == SCSI_LOW_WRITE)
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bcopy(sp->scp_data, bs->sc_bufp, bs->sc_seglen);
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}
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else
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{
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/* setup segaddr */
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bs->sc_segaddr = (u_int8_t *) phys;
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/* setup seglen */
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endva = (vaddr_t) round_page((vaddr_t) sp->scp_data + sp->scp_datalen);
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for (va = (vaddr_t) sp->scp_data; ; phys = nphys)
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{
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if ((va += BSHW_PAGE_SIZE) >= endva)
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{
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bs->sc_seglen = sp->scp_datalen;
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break;
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}
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nphys = vtophys(va);
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if (phys + BSHW_PAGE_SIZE != nphys || nphys >= bs->sc_minphys)
|
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{
|
|
bs->sc_seglen =
|
|
(u_int8_t *) trunc_page(va) - sp->scp_data;
|
|
break;
|
|
}
|
|
}
|
|
/* setup bufp */
|
|
bs->sc_bufp = NULL;
|
|
}
|
|
|
|
bshw_dmastart(ct);
|
|
cthw_set_count(chp, bs->sc_seglen);
|
|
ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
bshw_dma_xfer_stop(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct sc_p *sp = &slp->sl_scp;
|
|
struct bshw_softc *bs = ct->ct_hw;
|
|
struct targ_info *ti;
|
|
u_int count, transbytes;
|
|
|
|
bshw_dmadone(ct);
|
|
|
|
ti = slp->sl_Tnexus;
|
|
if (ti == NULL)
|
|
return;
|
|
|
|
if (ti->ti_phase == PH_DATA)
|
|
{
|
|
count = cthw_get_count(&ct->sc_ch);
|
|
if (count < (u_int) bs->sc_seglen)
|
|
{
|
|
transbytes = bs->sc_seglen - count;
|
|
if (bs->sc_bufp != NULL &&
|
|
sp->scp_direction == SCSI_LOW_READ)
|
|
bcopy(bs->sc_bufp, sp->scp_data, transbytes);
|
|
|
|
sp->scp_data += transbytes;
|
|
sp->scp_datalen -= transbytes;
|
|
}
|
|
else if (count > (u_int) bs->sc_seglen)
|
|
{
|
|
printf("%s: port data %x != seglen %x\n",
|
|
slp->sl_xname, count, bs->sc_seglen);
|
|
slp->sl_error |= PDMAERR;
|
|
}
|
|
|
|
scsi_low_data_finish(slp);
|
|
}
|
|
else
|
|
{
|
|
printf("%s: extra DMA interrupt\n", slp->sl_xname);
|
|
slp->sl_error |= PDMAERR;
|
|
}
|
|
|
|
bs->sc_bufp = NULL;
|
|
}
|
|
|
|
/* common dma settings */
|
|
#undef DMA1_SMSK
|
|
#define DMA1_SMSK (0x15)
|
|
#undef DMA1_MODE
|
|
#define DMA1_MODE (0x17)
|
|
#undef DMA1_FFC
|
|
#define DMA1_FFC (0x19)
|
|
#undef DMA1_CHN
|
|
#define DMA1_CHN(c) (0x01 + ((c) << 2))
|
|
|
|
#define DMA37SM_SET 0x04
|
|
#define DMA37MD_WRITE 0x04
|
|
#define DMA37MD_READ 0x08
|
|
#define DMA37MD_SINGLE 0x40
|
|
|
|
static bus_addr_t dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 };
|
|
|
|
static __inline void
|
|
bshw_dma_write_1(chp, port, val)
|
|
struct ct_bus_access_handle *chp;
|
|
bus_addr_t port;
|
|
u_int8_t val;
|
|
{
|
|
|
|
CT_BUS_WEIGHT(chp);
|
|
outb(port, val);
|
|
}
|
|
|
|
static void
|
|
bshw_dmastart(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct bshw_softc *bs = ct->ct_hw;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
int chan = bs->sc_drq;
|
|
bus_addr_t waport;
|
|
u_int8_t regv, *phys = bs->sc_segaddr;
|
|
u_int nbytes = bs->sc_seglen;
|
|
|
|
/* flush cpu cache */
|
|
(*bs->sc_dmasync_before) (ct);
|
|
|
|
/*
|
|
* Program one of DMA channels 0..3. These are
|
|
* byte mode channels.
|
|
*/
|
|
/* set dma channel mode, and reset address ff */
|
|
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
|
|
regv = DMA37MD_WRITE | DMA37MD_SINGLE | chan;
|
|
else
|
|
regv = DMA37MD_READ | DMA37MD_SINGLE | chan;
|
|
|
|
bshw_dma_write_1(chp, DMA1_MODE, regv);
|
|
bshw_dma_write_1(chp, DMA1_FFC, 0);
|
|
|
|
/* send start address */
|
|
waport = DMA1_CHN(chan);
|
|
bshw_dma_write_1(chp, waport, (u_int) phys);
|
|
bshw_dma_write_1(chp, waport, ((u_int) phys) >> 8);
|
|
bshw_dma_write_1(chp, dmapageport[chan], ((u_int) phys) >> 16);
|
|
|
|
/* send count */
|
|
bshw_dma_write_1(chp, waport + 2, --nbytes);
|
|
bshw_dma_write_1(chp, waport + 2, nbytes >> 8);
|
|
|
|
/* vendor unique hook */
|
|
if (bs->sc_hw->hw_dma_start)
|
|
(*bs->sc_hw->hw_dma_start)(ct);
|
|
|
|
bshw_dma_write_1(chp, DMA1_SMSK, chan);
|
|
ct_cmdp_write_1(chp, CMDP_DMES);
|
|
}
|
|
|
|
static void
|
|
bshw_dmadone(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct bshw_softc *bs = ct->ct_hw;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
bshw_dma_write_1(chp, DMA1_SMSK, (bs->sc_drq | DMA37SM_SET));
|
|
ct_cmdp_write_1(chp, CMDP_DMER);
|
|
|
|
/* vendor unique hook */
|
|
if (bs->sc_hw->hw_dma_stop)
|
|
(*bs->sc_hw->hw_dma_stop) (ct);
|
|
|
|
/* flush cpu cache */
|
|
(*bs->sc_dmasync_after) (ct);
|
|
}
|
|
|
|
/**********************************************
|
|
* VENDOR UNIQUE DMA FUNCS
|
|
**********************************************/
|
|
static int bshw_dma_init_sc98(struct ct_softc *);
|
|
static void bshw_dma_start_sc98(struct ct_softc *);
|
|
static void bshw_dma_stop_sc98(struct ct_softc *);
|
|
static int bshw_dma_init_texa(struct ct_softc *);
|
|
static void bshw_dma_start_elecom(struct ct_softc *);
|
|
static void bshw_dma_stop_elecom(struct ct_softc *);
|
|
|
|
static int
|
|
bshw_dma_init_texa(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
u_int8_t regval;
|
|
|
|
if ((regval = ct_cr_read_1(chp, 0x37)) & 0x08)
|
|
return 0;
|
|
|
|
ct_cr_write_1(chp, 0x37, regval | 0x08);
|
|
regval = ct_cr_read_1(chp, 0x3f);
|
|
ct_cr_write_1(chp, 0x3f, regval | 0x08);
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
bshw_dma_init_sc98(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
if (ct_cr_read_1(chp, 0x37) & 0x08)
|
|
return 0;
|
|
|
|
/* If your card is SC98 with bios ver 1.01 or 1.02 under no PCI */
|
|
ct_cr_write_1(chp, 0x37, 0x1a);
|
|
ct_cr_write_1(chp, 0x3f, 0x1a);
|
|
#if 0
|
|
/* only valid for IO */
|
|
ct_cr_write_1(chp, 0x40, 0xf4);
|
|
ct_cr_write_1(chp, 0x41, 0x9);
|
|
ct_cr_write_1(chp, 0x43, 0xff);
|
|
ct_cr_write_1(chp, 0x46, 0x4e);
|
|
|
|
ct_cr_write_1(chp, 0x48, 0xf4);
|
|
ct_cr_write_1(chp, 0x49, 0x9);
|
|
ct_cr_write_1(chp, 0x4b, 0xff);
|
|
ct_cr_write_1(chp, 0x4e, 0x4e);
|
|
#endif
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
bshw_dma_start_sc98(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
ct_cr_write_1(chp, 0x73, 0x32);
|
|
ct_cr_write_1(chp, 0x74, 0x23);
|
|
}
|
|
|
|
static void
|
|
bshw_dma_stop_sc98(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
ct_cr_write_1(chp, 0x73, 0x43);
|
|
ct_cr_write_1(chp, 0x74, 0x34);
|
|
}
|
|
|
|
static void
|
|
bshw_dma_start_elecom(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
|
|
|
|
ct_cr_write_1(chp, 0x32, tmp & 0xdf);
|
|
}
|
|
|
|
static void
|
|
bshw_dma_stop_elecom(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
|
|
|
|
ct_cr_write_1(chp, 0x32, tmp | 0x20);
|
|
}
|
|
|
|
static struct bshw bshw_generic = {
|
|
BSHW_SYNC_RELOAD,
|
|
|
|
0,
|
|
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
};
|
|
|
|
static struct bshw bshw_sc98 = {
|
|
BSHW_DOUBLE_DMACHAN,
|
|
|
|
0x60,
|
|
|
|
bshw_dma_init_sc98,
|
|
bshw_dma_start_sc98,
|
|
bshw_dma_stop_sc98,
|
|
};
|
|
|
|
static struct bshw bshw_texa = {
|
|
BSHW_DOUBLE_DMACHAN,
|
|
|
|
0x60,
|
|
|
|
bshw_dma_init_texa,
|
|
NULL,
|
|
NULL,
|
|
};
|
|
|
|
static struct bshw bshw_elecom = {
|
|
0,
|
|
|
|
0x38,
|
|
|
|
NULL,
|
|
bshw_dma_start_elecom,
|
|
bshw_dma_stop_elecom,
|
|
};
|
|
|
|
static struct bshw bshw_lc_smit = {
|
|
BSHW_SMFIFO | BSHW_DOUBLE_DMACHAN,
|
|
|
|
0x60,
|
|
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
};
|
|
|
|
static struct bshw bshw_lha20X = {
|
|
BSHW_DOUBLE_DMACHAN,
|
|
|
|
0x60,
|
|
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
};
|
|
|
|
/* hw tabs */
|
|
static dvcfg_hw_t bshw_hwsel_array[] = {
|
|
/* 0x00 */ &bshw_generic,
|
|
/* 0x01 */ &bshw_sc98,
|
|
/* 0x02 */ &bshw_texa,
|
|
/* 0x03 */ &bshw_elecom,
|
|
/* 0x04 */ &bshw_lc_smit,
|
|
/* 0x05 */ &bshw_lha20X,
|
|
};
|
|
|
|
struct dvcfg_hwsel bshw_hwsel = {
|
|
DVCFG_HWSEL_SZ(bshw_hwsel_array),
|
|
bshw_hwsel_array
|
|
};
|