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154 lines
6.9 KiB
C
154 lines
6.9 KiB
C
/*
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* Copyright (c) 1997 Ted Faber
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Ted Faber.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* PCI/CardBus Device IDs */
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#define PCI_DEVICE_ID_PCIC_OZ6729 0x67291217ul
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#define PCI_DEVICE_ID_PCIC_OZ6730 0x673A1217ul
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#define PCI_DEVICE_ID_PCIC_CLPD6729 0x11001013ul
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#define PCI_DEVICE_ID_PCIC_CLPD6832 0x11101013ul
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#define PCI_DEVICE_ID_PCIC_TI1130 0xac12104cul
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#define PCI_DEVICE_ID_PCIC_TI1131 0xac15104cul
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#define PCI_DEVICE_ID_PCIC_TI1211 0xac1e104cul
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#define PCI_DEVICE_ID_PCIC_TI1220 0xac17104cul
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#define PCI_DEVICE_ID_PCIC_TI1221 0xac19104cul
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#define PCI_DEVICE_ID_PCIC_TI1225 0xac1c104cul
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#define PCI_DEVICE_ID_PCIC_TI1250 0xac16104cul
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#define PCI_DEVICE_ID_PCIC_TI1251 0xac1d104cul
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#define PCI_DEVICE_ID_PCIC_TI1251B 0xac1f104cul
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#define PCI_DEVICE_ID_PCIC_TI1410 0xac50104cul
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#define PCI_DEVICE_ID_PCIC_TI1420 0xac51104cul
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#define PCI_DEVICE_ID_PCIC_TI1450 0xac1b104cul
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#define PCI_DEVICE_ID_PCIC_TI1451 0xac52104cul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a1179ul
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#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f1179ul
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#define PCI_DEVICE_ID_RICOH_RL5C465 0x04651180ul
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#define PCI_DEVICE_ID_RICOH_RL5C475 0x04751180ul
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#define PCI_DEVICE_ID_RICOH_RL5C476 0x04761180ul
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#define PCI_DEVICE_ID_RICOH_RL5C478 0x04781180ul
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/* CL-PD6832 CardBus defines */
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#define CLPD6832_IO_BASE0 0x002c
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#define CLPD6832_IO_LIMIT0 0x0030
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#define CLPD6832_IO_BASE1 0x0034
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#define CLPD6832_IO_LIMIT1 0x0038
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#define CLPD6832_BRIDGE_CONTROL 0x003c
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#define CLPD6832_LEGACY_16BIT_IOADDR 0x0044
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#define CLPD6832_LEGACY_16BIT_IOENABLE 0x0001
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#define CLPD6832_SOCKET 0x004c
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/* Configuration constants */
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#define CLPD6832_BCR_MGMT_IRQ_ENA 0x08000000
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#define CLPD6832_BCR_ISA_IRQ 0x00800000
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#define CLPD6832_COMMAND_DEFAULTS 0x00000045
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#define CLPD6832_NUM_REGS 2
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/* End of CL-PD6832 defines */
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/* Texas Instruments PCI-1130/1131 CardBus Controller */
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#define TI113X_PCI_SYSTEM_CONTROL 0x80 /* System Control */
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#define TI113X_PCI_RETRY_STATUS 0x90 /* Retry Status */
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#define TI113X_PCI_CARD_CONTROL 0x91 /* Card Control */
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#define TI113X_PCI_DEVICE_CONTROL 0x92 /* Device Control */
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#define TI113X_PCI_BUFFER_CONTROL 0x93 /* Buffer Control */
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#define TI113X_PCI_SOCKET_DMA0 0x94 /* Socket DMA Register 0 */
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#define TI113X_PCI_SOCKET_DMA1 0x98 /* Socket DMA Register 1 */
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/* Card control register (TI113X_SYSTEM_CONTROL == 0x80) */
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#define TI113X_SYSCNTL_VCC_PROTECT 0x00200000u
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#define TI113X_SYSCNTL_CLKRUN_SEL 0x00000080u
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#define TI113X_SYSCNTL_PWRSAVINGS 0x00000040u
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#define TI113X_SYSCNTL_KEEP_CLK 0x00000002u
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#define TI113X_SYSCNTL_CLKRUN_ENA 0x00000001u
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/* Card control register (TI113X_CARD_CONTROL == 0x91) */
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#define TI113X_CARDCNTL_RING_ENA 0x80u
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#define TI113X_CARDCNTL_ZOOM_VIDEO 0x40u
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#define TI113X_CARDCNTL_PCI_IRQ_ENA 0x20u
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#define TI113X_CARDCNTL_PCI_IREQ 0x10u
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#define TI113X_CARDCNTL_PCI_CSC 0x08u
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#define TI113X_CARDCNTL_MASK (TI113X_CARDCNTL_PCI_IRQ_ENA | TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
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#define TI113X_FUNC0_VALID TI113X_CARDCNTL_MASK
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#define TI113X_FUNC1_VALID (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
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/* Reserved bit 0x04u */
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#define TI113X_CARDCNTL_SPKR_ENA 0x02u
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#define TI113X_CARDCNTL_INT 0x01u
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/* Device control register (TI113X_DEVICE_CONTROL == 0x92) */
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#define TI113X_DEVCNTL_5V_SOCKET 0x40u
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#define TI113X_DEVCNTL_3V_SOCKET 0x20u
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#define TI113X_DEVCNTL_INTR_MASK 0x06u
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#define TI113X_DEVCNTL_INTR_NONE 0x00u
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#define TI113X_DEVCNTL_INTR_ISA 0x02u
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#define TI113X_DEVCNTL_INTR_SERIAL 0x04u
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/* TI112X specific code */
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#define TI12XX_DEVCNTL_INTR_ALLSERIAL 0x06u
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/* Texas Instruments PCI-1130/1131 CardBus Controller */
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#define TI113X_ExCA_IO_OFFSET0 0x36 /* Offset of I/O window */
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#define TI113X_ExCA_IO_OFFSET1 0x38 /* Offset of I/O window */
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#define TI113X_ExCA_MEM_WINDOW_PAGE 0x3C /* Memory Window Page */
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/* sanpei */
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/* For Bridge Control register (CB_PCI_BRIDGE_CTRL) */
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#define CB_BCR_CB_RESET 0x0040
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#define CB_BCR_INT_EXCA 0x0080
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/* PCI Configuration Registers (common) */
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#define CB_PCI_VENDOR_ID 0x00 /* vendor ID */
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#define CB_PCI_DEVICE_ID 0x02 /* device ID */
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#define CB_PCI_COMMAND 0x04 /* PCI command */
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#define CB_PCI_STATUS 0x06 /* PCI status */
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#define CB_PCI_REVISION_ID 0x08 /* PCI revision ID */
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#define CB_PCI_CLASS 0x09 /* PCI class code */
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#define CB_PCI_CACHE_LINE_SIZE 0x0c /* Cache line size */
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#define CB_PCI_LATENCY 0x0d /* PCI latency timer */
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#define CB_PCI_HEADER_TYPE 0x0e /* PCI header type */
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#define CB_PCI_BIST 0x0f /* Built-in self test */
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#define CB_PCI_SOCKET_BASE 0x10 /* Socket/ExCA base address reg. */
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#define CB_PCI_CB_STATUS 0x16 /* CardBus Status */
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#define CB_PCI_PCI_BUS_NUM 0x18 /* PCI bus number */
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#define CB_PCI_CB_BUS_NUM 0x19 /* CardBus bus number */
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#define CB_PCI_CB_SUB_BUS_NUM 0x1A /* Subordinate CardBus bus number */
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#define CB_PCI_CB_LATENCY 0x1A /* CardBus latency timer */
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#define CB_PCI_MEMBASE0 0x1C /* Memory base register 0 */
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#define CB_PCI_MEMLIMIT0 0x20 /* Memory limit register 0 */
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#define CB_PCI_MEMBASE1 0x24 /* Memory base register 1 */
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#define CB_PCI_MEMLIMIT1 0x28 /* Memory limit register 1 */
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#define CB_PCI_IOBASE0 0x2C /* I/O base register 0 */
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#define CB_PCI_IOLIMIT0 0x30 /* I/O limit register 0 */
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#define CB_PCI_IOBASE1 0x34 /* I/O base register 1 */
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#define CB_PCI_IOLIMIT1 0x38 /* I/O limit register 1 */
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#define CB_PCI_INT_LINE 0x3C /* Interrupt Line */
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#define CB_PCI_INT_PIN 0x3D /* Interrupt Pin */
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#define CB_PCI_BRIDGE_CTRL 0x3E /* Bridge Control */
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#define CB_PCI_SUBSYS_VENDOR_ID 0x40 /* Subsystem Vendor ID */
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#define CB_PCI_SUBSYS_ID 0x42 /* Subsystem ID */
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#define CB_PCI_LEGACY16_IOADDR 0x44 /* Legacy 16bit I/O address */
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#define CB_PCI_LEGACY16_IOENABLE 0x01 /* Enable Legacy 16bit I/O address */
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