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240 lines
7.8 KiB
C
240 lines
7.8 KiB
C
/***********************license start***************
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* Copyright (c) 2011 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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************************license end**************************************/
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/**
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* @file
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*
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* Interface to event profiler.
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*
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*/
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-interrupt.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-coremask.h"
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#include "cvmx-spinlock.h"
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#include "cvmx-atomic.h"
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#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
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#include "cvmx-error.h"
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#endif
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#include "cvmx-asm.h"
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#include "cvmx-bootmem.h"
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#include "cvmx-profiler.h"
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#ifdef PROFILER_DEBUG
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#define PRINTF(fmt, args...) cvmx_safe_printf(fmt, ##args)
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#else
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#define PRINTF(fmt, args...)
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#endif
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CVMX_SHARED static event_counter_control_block_t eccb;
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cvmx_config_block_t *pcpu_cfg_blk;
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int read_percpu_block = 1;
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/**
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* Set Interrupt IRQ line for Performance Counter
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*
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*/
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void cvmx_update_perfcnt_irq(void)
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{
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uint64_t cvmctl;
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/* Clear CvmCtl[IPPCI] bit and move the Performance Counter
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* interrupt to IRQ 6
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*/
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CVMX_MF_COP0(cvmctl, COP0_CVMCTL);
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cvmctl &= ~(7 << 7);
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cvmctl |= 6 << 7;
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CVMX_MT_COP0(cvmctl, COP0_CVMCTL);
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}
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/**
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* @INTERNAL
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* Return the baseaddress of the namedblock
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* @param buf_name Name of Namedblock
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*
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* @return baseaddress of block on Success, NULL on failure.
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*/
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static
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void *cvmx_get_memory_addr(const char* buf_name)
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{
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void *buffer_ptr = NULL;
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const struct cvmx_bootmem_named_block_desc *block_desc = cvmx_bootmem_find_named_block(buf_name);
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if (block_desc)
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buffer_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
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assert (buffer_ptr != NULL);
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return buffer_ptr;
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}
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/**
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* @INTERNAL
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* Initialize the cpu block metadata.
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*
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* @param cpu core no
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* @param size size of per cpu memory in named block
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*
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*/
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static
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void cvmx_init_pcpu_block(int cpu, int size)
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{
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eccb.cfg_blk.pcpu_base_addr[cpu] = (char *)cvmx_get_memory_addr(EVENT_BUFFER_BLOCK) + (size * cpu);
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assert (eccb.cfg_blk.pcpu_base_addr[cpu] != NULL);
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cvmx_ringbuf_t *cpu_buf = (cvmx_ringbuf_t *) eccb.cfg_blk.pcpu_base_addr[cpu];
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cpu_buf->pcpu_blk_info.size = size;
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cpu_buf->pcpu_blk_info.max_samples = ((size - sizeof(cvmx_cpu_event_block_t)) / sizeof(cvmx_sample_entry_t));
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cpu_buf->pcpu_blk_info.sample_count = 0;
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cpu_buf->pcpu_blk_info.sample_read = 0;
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cpu_buf->pcpu_blk_info.data = eccb.cfg_blk.pcpu_base_addr[cpu] + sizeof(cvmx_cpu_event_block_t) + PADBYTES;
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cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.tail = \
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cpu_buf->pcpu_data = cpu_buf->pcpu_blk_info.data;
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cpu_buf->pcpu_blk_info.end = eccb.cfg_blk.pcpu_base_addr[cpu] + size;
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cvmx_atomic_set32(&read_percpu_block, 0);
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/*
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* Write per cpu mem base address info in to 'event config' named block,
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* This info is needed by oct-remote-profile to get Per cpu memory
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* base address of each core of the named block.
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*/
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pcpu_cfg_blk = (cvmx_config_block_t *) eccb.config_blk_base_addr;
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pcpu_cfg_blk->pcpu_base_addr[cpu] = eccb.cfg_blk.pcpu_base_addr[cpu];
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}
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/**
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* @INTERNAL
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* Retrieve the info from the 'event_config' named block.
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*
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* Here events value is read(as passed to oct-remote-profile) to reset perf
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* counters on every Perf counter overflow.
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*
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*/
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static
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void cvmx_read_config_blk(void)
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{
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eccb.config_blk_base_addr = (char *)cvmx_get_memory_addr(EVENT_BUFFER_CONFIG_BLOCK);
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memcpy(&(eccb.cfg_blk.events), eccb.config_blk_base_addr + \
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offsetof(cvmx_config_block_t, events), sizeof(int64_t));
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cvmx_atomic_set32(&eccb.read_cfg_blk,1);
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PRINTF("cfg_blk.events=%lu, sample_count=%ld\n", eccb.cfg_blk.events, eccb.cfg_blk.sample_count);
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}
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/**
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* @INTERNAL
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* Add new sample to the buffer and increment the head pointer and
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* global sample count(i.e sum total of samples collected on all cores)
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*
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*/
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static
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void cvmx_add_sample_to_buffer(void)
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{
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uint32_t epc;
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int cpu = cvmx_get_core_num();
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CVMX_MF_COP0(epc, COP0_EPC);
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cvmx_ringbuf_t *cpu_buf = (cvmx_ringbuf_t *) eccb.cfg_blk.pcpu_base_addr[cpu];
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/*
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* head/tail pointer can be NULL, and this case arises when oct-remote-profile is
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* invoked afresh. To keep memory sane for current instance, we clear namedblock off
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* previous data and this is accomplished by octeon_remote_write_mem from host.
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*/
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if (cvmx_unlikely(!cpu_buf->pcpu_blk_info.head && !cpu_buf->pcpu_blk_info.end)) {
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/* Reread the event count as a different threshold val could be
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* passed with profiler alongside --events flag */
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cvmx_read_config_blk();
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cvmx_init_pcpu_block(cpu, EVENT_PERCPU_BUFFER_SIZE);
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}
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/* In case of hitting end of buffer, reset head,data ptr to start */
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if (cpu_buf->pcpu_blk_info.head == cpu_buf->pcpu_blk_info.end)
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cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.data = cpu_buf->pcpu_data;
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/* Store the pc, respective core no.*/
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cvmx_sample_entry_t *sample = (cvmx_sample_entry_t *) cpu_buf->pcpu_blk_info.data;
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sample->pc = epc;
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sample->core = cpu;
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/* Update Per CPU stats */
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cpu_buf->pcpu_blk_info.sample_count++;
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cpu_buf->pcpu_blk_info.data += sizeof(cvmx_sample_entry_t);
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cpu_buf->pcpu_blk_info.head = cpu_buf->pcpu_blk_info.data;
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/* Increment the global sample count i.e sum total of samples on all cores*/
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cvmx_atomic_add64(&(pcpu_cfg_blk->sample_count), 1);
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PRINTF("the core%d:pc 0x%016lx, sample_count=%ld\n", cpu, sample->pc, cpu_buf->pcpu_blk_info.sample_count);
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}
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/**
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* @INTERNAL
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* Reset performance counters
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*
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* @param pf The performance counter Number (0, 1)
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* @param events The threshold value for which interrupt has to be asserted
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*/
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static
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void cvmx_reset_perf_counter(int pf, uint64_t events)
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{
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uint64_t pfc;
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pfc = (1ull << 63) - events;
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if (!pf) {
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CVMX_MT_COP0(pfc, COP0_PERFVALUE0);
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} else
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CVMX_MT_COP0(pfc, COP0_PERFVALUE1);
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}
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void cvmx_collect_sample(void)
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{
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if (!eccb.read_cfg_blk)
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cvmx_read_config_blk();
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if (read_percpu_block)
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cvmx_init_pcpu_block(cvmx_get_core_num(), EVENT_PERCPU_BUFFER_SIZE);
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cvmx_add_sample_to_buffer();
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cvmx_reset_perf_counter(0, eccb.cfg_blk.events);
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}
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