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dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
749 lines
34 KiB
C
749 lines
34 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the Trace buffer hardware.
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*
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* WRITING THE TRACE BUFFER
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*
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* When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once
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* (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled
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* by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC
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* commands that are traced is determined by the filter and the two triggers, each of which is comprised of
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* masks for command, sid, did, and address). If triggers are disabled, then only those commands matching
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* the filter are traced. If triggers are enabled, then only those commands matching the filter, the start
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* trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger.
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*
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* For a given command, its XMC data is written immediately to the buffer. If the command has XMD data,
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* then that data comes in-order at some later time. The XMD data is accumulated across all valid
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* XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer
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* as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC
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* data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost.
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*
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*
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* READING THE TRACE BUFFER
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*
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* Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order,
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* as soon as it has access to the (single-ported) trace buffer.
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*
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* On Octeon2, each entry of the trace buffer is read by two CSR memory read operations. The first read accesses
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* bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer
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* services each read in order, as soon as it has access to the (single-ported) trace buffer. Buffer's read pointer
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* increments after two CSR memory read operations.
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*
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*
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* OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
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*
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* The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow
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* conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write
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* (traced event) increments the write pointer and each read increments the read pointer. During the overflow
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* condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is
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* resolved. The first entry that is written immediately following the overflow condition may be marked to
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* indicate that a tracing discontinuity has occurred before this entry. During the underflow condition,
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* reading does not increment the read pointer and the read data is marked to indicate that no read data is
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* available.
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*
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* The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4).
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* "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the
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* absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs
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* every time the desired level of "fullness" is achieved.
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*
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*
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* Trace buffer entry format
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* @verbatim
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* 6 5 4 3 2 1 0
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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*
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* Trace buffer entry format in Octeon2 is different
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*
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* 6 5 4 3 2 1 0
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* 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[37:0] | 0 | src id | Group 1 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[37:0] | 0 | xmd mask | src id | Group 2 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| address[37:0] | 0 |s-did| dest id | src id | Group 3 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |sta| *address[37:3] | *Length | dest id | src id | Group 4 | diff timestamp|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* notes:
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* - diff timestamp is the difference in time from the previous trace event to this event - 1. the granularity of the timestamp is programmable
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* - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the
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* XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
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* - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
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* 0x0=not valid
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* 0x1=valid, no discontinuity
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* 0x2=not valid, discontinuity
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* 0x3=valid, discontinuity
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* - commands are encoded as follows:
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* 0x0=DWB
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* 0x1=PL2
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* 0x2=PSL1
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* 0x3=LDD
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* 0x4=LDI
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* 0x5=LDT
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* 0x6=STF
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* 0x7=STC
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* 0x8=STP
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* 0x9=STT
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* 0xa=IOBLD8
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* 0xb=IOBLD16
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* 0xc=IOBLD32
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* 0xd=IOBLD64
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* 0xe=IOBST
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* 0xf=IOBDMA
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* - In Octeon2 the commands are grouped as follows:
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* Group1:
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* XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2,
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* XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64,
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* XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64,
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* XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64,
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* XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64
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* Group2:
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* XMC_STF, XMC_STT, XMC_STP, XMC_STC,
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* XMC_LDD, XMC_PSL1
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* XMC_SAA32, XMC_SAA64,
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* XMC_FAA32, XMC_FAA64,
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* XMC_FAS32, XMC_FAS64
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* Group3:
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* XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64,
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* XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64
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* Group4:
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* XMC_IOBDMA
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* - For non IOB* commands
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* - source id is encoded as follows:
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* 0x00-0x0f=PP[n]
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* 0x10=IOB(Packet)
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* 0x11=IOB(PKO)
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* 0x12=IOB(ReqLoad, ReqStore)
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* 0x13=IOB(DWB)
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* 0x14-0x1e=illegal
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* 0x1f=IOB(generic)
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* - dest id is unused (can only be L2c)
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* - For IOB* commands
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* - source id is encoded as follows:
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* 0x00-0x0f = PP[n]
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* - dest id is encoded as follows:
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* 0 = CIU/GPIO (for CSRs)
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* 1-2 = illegal
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* 3 = PCIe (access to RSL-type CSRs)
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* 4 = KEY (read/write operations)
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* 5 = FPA (free pool allocate/free operations)
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* 6 = DFA
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* 7 = ZIP (doorbell operations)
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* 8 = RNG (load/IOBDMA operations)
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* 10 = PKO (doorbell operations)
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* 11 = illegal
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* 12 = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations)
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* 13-31 = illegal
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* @endverbatim
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*
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* <hr>$Revision: 70030 $<hr>
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*/
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#ifndef __CVMX_TRA_H__
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#define __CVMX_TRA_H__
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#include "cvmx.h"
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#include "cvmx-l2c.h"
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include "cvmx-tra-defs.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* CSR typedefs have been moved to cvmx-tra-defs.h */
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/* The 'saa' filter command is renamed as 'saa64' */
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#define CVMX_TRA_FILT_SAA CVMX_TRA_FILT_SAA64
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/* The 'iobst' filter command is renamed as 'iobst64' */
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#define CVMX_TRA_FILT_IOBST CVMX_TRA_FILT_IOBST64
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/**
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* Enumeration of the bitmask of all the filter commands. The bit positions
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* correspond to Octeon2 model.
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*/
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typedef enum
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{
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CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */
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CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */
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CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */
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CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */
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CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */
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CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */
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CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */
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CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */
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CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */
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CVMX_TRA_FILT_STF = 1ull<<16, /**< full block store to L2, fill 0's */
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CVMX_TRA_FILT_STT = 1ull<<17, /**< full block store bypass-L2, fill 0's */
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CVMX_TRA_FILT_STP = 1ull<<18, /**< partial store to L2 */
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CVMX_TRA_FILT_STC = 1ull<<19, /**< partial store to L2, if duptag valid */
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CVMX_TRA_FILT_STFIL1 = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */
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CVMX_TRA_FILT_STTIL1 = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */
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CVMX_TRA_FILT_FAS32 = 1ull<<22, /**< to load from and write a word of memory atomically */
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CVMX_TRA_FILT_FAS64 = 1ull<<23, /**< to load from and write a doubleword of memory atomically */
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CVMX_TRA_FILT_WBIL2I = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */
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CVMX_TRA_FILT_LTGL2I = 1ull<<25, /**< read tag @ index/way into CSR */
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CVMX_TRA_FILT_STGL2I = 1ull<<26, /**< write tag @ index/way from CSR */
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CVMX_TRA_FILT_INVL2 = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */
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CVMX_TRA_FILT_WBIL2 = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */
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CVMX_TRA_FILT_WBL2 = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */
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CVMX_TRA_FILT_LCKL2 = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */
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CVMX_TRA_FILT_IOBLD8 = 1ull<<32, /**< load reflection 8bit */
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CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */
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CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */
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CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */
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CVMX_TRA_FILT_IOBST8 = 1ull<<36, /**< store reflection 8bit */
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CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */
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CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */
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CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */
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CVMX_TRA_FILT_SET8 = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */
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CVMX_TRA_FILT_SET16 = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */
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CVMX_TRA_FILT_SET32 = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */
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CVMX_TRA_FILT_SET64 = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */
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CVMX_TRA_FILT_CLR8 = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */
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CVMX_TRA_FILT_CLR16 = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */
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CVMX_TRA_FILT_CLR32 = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */
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CVMX_TRA_FILT_CLR64 = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */
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CVMX_TRA_FILT_INCR8 = 1ull<<48, /**< to load and increment 8bit of memory atomically */
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CVMX_TRA_FILT_INCR16 = 1ull<<49, /**< to load and increment 16bit of memory atomically */
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CVMX_TRA_FILT_INCR32 = 1ull<<50, /**< to load and increment 32bit of memory atomically */
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CVMX_TRA_FILT_INCR64 = 1ull<<51, /**< to load and increment 64bit of memory atomically */
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CVMX_TRA_FILT_DECR8 = 1ull<<52, /**< to load and decrement 8bit of memory atomically */
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CVMX_TRA_FILT_DECR16 = 1ull<<53, /**< to load and decrement 16bit of memory atomically */
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CVMX_TRA_FILT_DECR32 = 1ull<<54, /**< to load and decrement 32bit of memory atomically */
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CVMX_TRA_FILT_DECR64 = 1ull<<55, /**< to load and decrement 64bit of memory atomically */
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CVMX_TRA_FILT_FAA32 = 1ull<<58, /**< to load from and add to a word of memory atomically */
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CVMX_TRA_FILT_FAA64 = 1ull<<59, /**< to load from and add to a doubleword of memory atomically */
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CVMX_TRA_FILT_SAA32 = 1ull<<62, /**< to atomically add a word to a memory location */
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CVMX_TRA_FILT_SAA64 = 1ull<<63, /**< to atomically add a doubleword to a memory location */
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CVMX_TRA_FILT_ALL = -1ull /**< all the above filter commands */
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} cvmx_tra_filt_t;
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/*
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* Enumeration of the bitmask of all source commands.
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*/
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typedef enum
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{
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CVMX_TRA_SID_PP0 = 1ull<<0, /**< Enable tracing from PP0 with matching sourceID */
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CVMX_TRA_SID_PP1 = 1ull<<1, /**< Enable tracing from PP1 with matching sourceID */
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CVMX_TRA_SID_PP2 = 1ull<<2, /**< Enable tracing from PP2 with matching sourceID */
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CVMX_TRA_SID_PP3 = 1ull<<3, /**< Enable tracing from PP3 with matching sourceID */
|
|
CVMX_TRA_SID_PP4 = 1ull<<4, /**< Enable tracing from PP4 with matching sourceID */
|
|
CVMX_TRA_SID_PP5 = 1ull<<5, /**< Enable tracing from PP5 with matching sourceID */
|
|
CVMX_TRA_SID_PP6 = 1ull<<6, /**< Enable tracing from PP6 with matching sourceID */
|
|
CVMX_TRA_SID_PP7 = 1ull<<7, /**< Enable tracing from PP7 with matching sourceID */
|
|
CVMX_TRA_SID_PP8 = 1ull<<8, /**< Enable tracing from PP8 with matching sourceID */
|
|
CVMX_TRA_SID_PP9 = 1ull<<9, /**< Enable tracing from PP9 with matching sourceID */
|
|
CVMX_TRA_SID_PP10 = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */
|
|
CVMX_TRA_SID_PP11 = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */
|
|
CVMX_TRA_SID_PP12 = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */
|
|
CVMX_TRA_SID_PP13 = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */
|
|
CVMX_TRA_SID_PP14 = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */
|
|
CVMX_TRA_SID_PP15 = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */
|
|
CVMX_TRA_SID_PKI = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */
|
|
CVMX_TRA_SID_PKO = 1ull<<17, /**< Enable tracing of write requests from PKO */
|
|
CVMX_TRA_SID_IOBREQ = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */
|
|
CVMX_TRA_SID_DWB = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */
|
|
CVMX_TRA_SID_ALL = -1ull /**< Enable tracing all the above source commands */
|
|
} cvmx_tra_sid_t;
|
|
|
|
|
|
#define CVMX_TRA_DID_SLI CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */
|
|
/*
|
|
* Enumeration of the bitmask of all destination commands.
|
|
*/
|
|
typedef enum
|
|
{
|
|
CVMX_TRA_DID_MIO = 1ull<<0, /**< Enable tracing of CIU and GPIO CSR's */
|
|
CVMX_TRA_DID_PCI = 1ull<<3, /**< Enable tracing of requests to PCI and RSL type CSR's */
|
|
CVMX_TRA_DID_KEY = 1ull<<4, /**< Enable tracing of requests to KEY memory */
|
|
CVMX_TRA_DID_FPA = 1ull<<5, /**< Enable tracing of requests to FPA */
|
|
CVMX_TRA_DID_DFA = 1ull<<6, /**< Enable tracing of requests to DFA */
|
|
CVMX_TRA_DID_ZIP = 1ull<<7, /**< Enable tracing of requests to ZIP */
|
|
CVMX_TRA_DID_RNG = 1ull<<8, /**< Enable tracing of requests to RNG */
|
|
CVMX_TRA_DID_IPD = 1ull<<9, /**< Enable tracing of IPD CSR accesses */
|
|
CVMX_TRA_DID_PKO = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */
|
|
CVMX_TRA_DID_POW = 1ull<<12, /**< Enable tracing of requests to RNG */
|
|
CVMX_TRA_DID_USB0 = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */
|
|
CVMX_TRA_DID_RAD = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */
|
|
CVMX_TRA_DID_DPI = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */
|
|
CVMX_TRA_DID_FAU = 1ull<<30, /**< Enable tracing FAU accesses */
|
|
CVMX_TRA_DID_ALL = -1ull /**< Enable tracing all the above destination commands */
|
|
} cvmx_tra_did_t;
|
|
|
|
/**
|
|
* TRA data format definition. Use the type field to
|
|
* determine which union element to use.
|
|
*
|
|
* In Octeon 2, the trace buffer is 69 bits,
|
|
* the first read accesses bits 63:0 of the trace buffer entry, and
|
|
* the second read accesses bits 68:64 of the trace buffer entry.
|
|
*/
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t datahi;
|
|
uint64_t data;
|
|
#else
|
|
uint64_t data;
|
|
uint64_t datahi;
|
|
#endif
|
|
} u128;
|
|
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved3 : 64;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t address : 36;
|
|
uint64_t reserved : 5;
|
|
uint64_t source : 5;
|
|
uint64_t reserved2 : 3;
|
|
uint64_t type : 5;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 5;
|
|
uint64_t reserved2 : 3;
|
|
uint64_t source : 5;
|
|
uint64_t reserved : 5;
|
|
uint64_t address : 36;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t reserved3 : 64;
|
|
#endif
|
|
} cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved3 : 64;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t address : 33;
|
|
uint64_t mask : 8;
|
|
uint64_t source : 5;
|
|
uint64_t reserved2 : 3;
|
|
uint64_t type : 5;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 5;
|
|
uint64_t reserved2 : 3;
|
|
uint64_t source : 5;
|
|
uint64_t mask : 8;
|
|
uint64_t address : 33;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t reserved3 : 64;
|
|
#endif
|
|
} store; /**< STC, STF, STP, STT */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved3 : 64;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t address : 36;
|
|
uint64_t reserved : 2;
|
|
uint64_t subid : 3;
|
|
uint64_t source : 4;
|
|
uint64_t dest : 5;
|
|
uint64_t type : 4;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 4;
|
|
uint64_t dest : 5;
|
|
uint64_t source : 4;
|
|
uint64_t subid : 3;
|
|
uint64_t reserved : 2;
|
|
uint64_t address : 36;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t reserved3 : 64;
|
|
#endif
|
|
} iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved3 : 64;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t address : 33;
|
|
uint64_t mask : 8;
|
|
uint64_t source : 4;
|
|
uint64_t dest : 5;
|
|
uint64_t type : 4;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 4;
|
|
uint64_t dest : 5;
|
|
uint64_t source : 4;
|
|
uint64_t mask : 8;
|
|
uint64_t address : 33;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t reserved3 : 64;
|
|
#endif
|
|
} iob; /**< for IOBDMA */
|
|
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved1 : 59;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
|
|
uint64_t addresslo : 35; /* and lower 64-bits. */
|
|
uint64_t reserved : 10;
|
|
uint64_t source : 5;
|
|
uint64_t type : 6;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 6;
|
|
uint64_t source : 5;
|
|
uint64_t reserved : 10;
|
|
uint64_t addresslo : 35;
|
|
uint64_t addresshi : 3;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t reserved1 : 59;
|
|
#endif
|
|
} cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, WBIL2i, LTGL2i, STGL2i, INVL2, WBIL2, LCKL2, SET*, CLR*, INCR*, DECR* */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved1 : 59;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
|
|
uint64_t addresslo : 35; /* and lower 64-bits */
|
|
uint64_t reserved : 2;
|
|
uint64_t mask : 8;
|
|
uint64_t source : 5;
|
|
uint64_t type : 6;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 6;
|
|
uint64_t source : 5;
|
|
uint64_t mask : 8;
|
|
uint64_t reserved : 2;
|
|
uint64_t addresslo : 35;
|
|
uint64_t addresshi : 3;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t reserved1 : 59;
|
|
#endif
|
|
} store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64, STTIL1, STFIL1 */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved1 : 59;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
|
|
uint64_t addresslo : 35; /* and lower 64-bits */
|
|
uint64_t reserved : 2;
|
|
uint64_t subid : 3;
|
|
uint64_t dest : 5;
|
|
uint64_t source : 5;
|
|
uint64_t type : 6;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 6;
|
|
uint64_t source : 5;
|
|
uint64_t dest : 5;
|
|
uint64_t subid : 3;
|
|
uint64_t reserved : 2;
|
|
uint64_t addresslo : 35;
|
|
uint64_t addresshi : 3;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t reserved1 : 59;
|
|
#endif
|
|
} iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */
|
|
struct
|
|
{
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved1 : 59;
|
|
uint64_t discontinuity:1;
|
|
uint64_t valid : 1;
|
|
uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
|
|
uint64_t addresslo : 32; /* and lower 64-bits */
|
|
uint64_t mask : 8;
|
|
uint64_t dest : 5;
|
|
uint64_t source : 5;
|
|
uint64_t type : 6;
|
|
uint64_t timestamp : 8;
|
|
#else
|
|
uint64_t timestamp : 8;
|
|
uint64_t type : 6;
|
|
uint64_t source : 5;
|
|
uint64_t dest : 5;
|
|
uint64_t mask : 8;
|
|
uint64_t addresslo : 32;
|
|
uint64_t addresshi : 3;
|
|
uint64_t valid : 1;
|
|
uint64_t discontinuity:1;
|
|
uint64_t reserved1 : 59;
|
|
#endif
|
|
} iob2; /**< for IOBDMA */
|
|
} cvmx_tra_data_t;
|
|
|
|
/* The trace buffer number to use. */
|
|
extern int _cvmx_tra_unit;
|
|
|
|
/**
|
|
* Setup the TRA buffer for use
|
|
*
|
|
* @param control TRA control setup
|
|
* @param filter Which events to log
|
|
* @param source_filter
|
|
* Source match
|
|
* @param dest_filter
|
|
* Destination match
|
|
* @param address Address compare
|
|
* @param address_mask
|
|
* Address mask
|
|
*/
|
|
extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
|
|
cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
|
|
uint64_t address, uint64_t address_mask);
|
|
|
|
/**
|
|
* Setup each TRA buffer for use
|
|
*
|
|
* @param tra Which TRA buffer to use (0-3)
|
|
* @param control TRA control setup
|
|
* @param filter Which events to log
|
|
* @param source_filter
|
|
* Source match
|
|
* @param dest_filter
|
|
* Destination match
|
|
* @param address Address compare
|
|
* @param address_mask
|
|
* Address mask
|
|
*/
|
|
extern void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
|
|
cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
|
|
uint64_t address, uint64_t address_mask);
|
|
|
|
/**
|
|
* Setup a TRA trigger. How the triggers are used should be
|
|
* setup using cvmx_tra_setup.
|
|
*
|
|
* @param trigger Trigger to setup (0 or 1)
|
|
* @param filter Which types of events to trigger on
|
|
* @param source_filter
|
|
* Source trigger match
|
|
* @param dest_filter
|
|
* Destination trigger match
|
|
* @param address Trigger address compare
|
|
* @param address_mask
|
|
* Trigger address mask
|
|
*/
|
|
extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
|
|
cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
|
|
uint64_t address, uint64_t address_mask);
|
|
|
|
/**
|
|
* Setup each TRA trigger. How the triggers are used should be
|
|
* setup using cvmx_tra_setup.
|
|
*
|
|
* @param tra Which TRA buffer to use (0-3)
|
|
* @param trigger Trigger to setup (0 or 1)
|
|
* @param filter Which types of events to trigger on
|
|
* @param source_filter
|
|
* Source trigger match
|
|
* @param dest_filter
|
|
* Destination trigger match
|
|
* @param address Trigger address compare
|
|
* @param address_mask
|
|
* Trigger address mask
|
|
*/
|
|
extern void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter,
|
|
cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
|
|
uint64_t address, uint64_t address_mask);
|
|
|
|
/**
|
|
* Read an entry from the TRA buffer. The trace buffer format is
|
|
* different in Octeon2, need to read twice from TRA_READ_DAT.
|
|
*
|
|
* @return Value return. High bit will be zero if there wasn't any data
|
|
*/
|
|
extern cvmx_tra_data_t cvmx_tra_read(void);
|
|
|
|
/**
|
|
* Read an entry from the TRA buffer from a given TRA unit.
|
|
*
|
|
* @param tra_unit Trace buffer unit to read
|
|
*
|
|
* @return Value return. High bit will be zero if there wasn't any data
|
|
*/
|
|
cvmx_tra_data_t cvmx_tra_read_v2(int tra_unit);
|
|
|
|
/**
|
|
* Decode a TRA entry into human readable output
|
|
*
|
|
* @param tra_ctl Trace control setup
|
|
* @param data Data to decode
|
|
*/
|
|
extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
|
|
|
|
/**
|
|
* Display the entire trace buffer. It is advised that you
|
|
* disable the trace buffer before calling this routine
|
|
* otherwise it could infinitely loop displaying trace data
|
|
* that it created.
|
|
*/
|
|
extern void cvmx_tra_display(void);
|
|
|
|
/**
|
|
* Display the entire trace buffer. It is advised that you
|
|
* disable the trace buffer before calling this routine
|
|
* otherwise it could infinitely loop displaying trace data
|
|
* that it created.
|
|
*
|
|
* @param tra_unit Which TRA buffer to use.
|
|
*/
|
|
extern void cvmx_tra_display_v2(int tra_unit);
|
|
|
|
/**
|
|
* Enable or disable the TRA hardware, by default enables all TRAs.
|
|
*
|
|
* @param enable 1=enable, 0=disable
|
|
*/
|
|
static inline void cvmx_tra_enable(int enable)
|
|
{
|
|
cvmx_tra_ctl_t control;
|
|
int tad;
|
|
|
|
for (tad = 0; tad < CVMX_L2C_TADS; tad++)
|
|
{
|
|
control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad));
|
|
control.s.ena = enable;
|
|
cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64);
|
|
cvmx_read_csr(CVMX_TRAX_CTL(tad));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Enable or disable a particular TRA hardware
|
|
*
|
|
* @param enable 1=enable, 0=disable
|
|
* @param tra which TRA to enable, CN68XX has 4.
|
|
*/
|
|
static inline void cvmx_tra_enable_v2(int enable, int tra)
|
|
{
|
|
cvmx_tra_ctl_t control;
|
|
|
|
if ((tra + 1) > CVMX_L2C_TADS)
|
|
{
|
|
cvmx_dprintf("cvmx_tra_enable: Invalid TRA(%d), max allowed are %d\n", tra, CVMX_L2C_TADS - 1);
|
|
tra = 0;
|
|
}
|
|
control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra));
|
|
control.s.ena = enable;
|
|
cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64);
|
|
cvmx_read_csr(CVMX_TRAX_CTL(tra));
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|
|
|