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dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
171 lines
5.7 KiB
C
171 lines
5.7 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <linux/module.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-clock.h>
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#include <asm/octeon/cvmx-uart.h>
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#else
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#include "cvmx.h"
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#include "cvmx-uart.h"
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#include "cvmx-interrupt.h"
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#endif
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#ifndef CVMX_BUILD_FOR_TOOLCHAIN
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void cvmx_uart_enable_intr(int uart, cvmx_uart_intr_handler_t handler)
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{
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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cvmx_uart_ier_t ier;
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cvmx_interrupt_register(CVMX_IRQ_UART0 + uart, handler, NULL);
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/* Enable uart interrupts for debugger Control-C processing */
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ier.u64 = cvmx_read_csr(CVMX_MIO_UARTX_IER(uart));
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ier.s.erbfi = 1;
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cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64);
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cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0 + uart);
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#endif
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}
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#endif
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static int cvmx_uart_simulator_p(void)
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{
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#ifndef CVMX_BUILD_FOR_TOOLCHAIN
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return cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM;
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#else
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extern int __octeon_simulator_p;
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return __octeon_simulator_p;
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#endif
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}
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/**
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* Function that does the real work of setting up the Octeon uart.
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* Takes all parameters as arguments, so it does not require gd
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* structure to be set up.
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*
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* @param uart_index Index of uart to configure
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* @param cpu_clock_hertz
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* CPU clock frequency in Hz
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* @param baudrate Baudrate to configure
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*
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* @return 0 on success
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* !0 on error
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*/
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int cvmx_uart_setup2(int uart_index, int cpu_clock_hertz, int baudrate)
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{
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uint16_t divisor;
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cvmx_uart_fcr_t fcrval;
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cvmx_uart_mcr_t mcrval;
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cvmx_uart_lcr_t lcrval;
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fcrval.u64 = 0;
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fcrval.s.en = 1; /* enable the FIFO's */
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fcrval.s.rxfr = 1; /* reset the RX fifo */
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fcrval.s.txfr = 1; /* reset the TX fifo */
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if (cvmx_uart_simulator_p())
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divisor = 1;
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else
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divisor = ((unsigned long)(cpu_clock_hertz + 8 * baudrate) / (unsigned long)(16 * baudrate));
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cvmx_write_csr(CVMX_MIO_UARTX_FCR(uart_index), fcrval.u64);
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mcrval.u64 = 0;
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if (uart_index == 1 && cvmx_uart_simulator_p())
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mcrval.s.afce = 1; /* enable auto flow control for simulator. Needed for gdb regression callfuncs.exp. */
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else
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mcrval.s.afce = 0; /* disable auto flow control so board can power on without serial port connected */
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mcrval.s.rts = 1; /* looks like this must be set for auto flow control to work */
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cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart_index));
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lcrval.u64 = 0;
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lcrval.s.cls = CVMX_UART_BITS8;
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lcrval.s.stop = 0; /* stop bit included? */
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lcrval.s.pen = 0; /* no parity? */
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lcrval.s.eps = 1; /* even parity? */
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lcrval.s.dlab = 1; /* temporary to program the divisor */
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cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64);
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cvmx_write_csr(CVMX_MIO_UARTX_DLL(uart_index), divisor & 0xff);
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cvmx_write_csr(CVMX_MIO_UARTX_DLH(uart_index), (divisor>>8) & 0xff);
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lcrval.s.dlab = 0; /* divisor is programmed now, set this back to normal */
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cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64);
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/* spec says need to wait after you program the divisor */
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if (!cvmx_uart_simulator_p())
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{
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uint64_t read_cycle;
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CVMX_MF_CYCLE (read_cycle);
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read_cycle += (2 * divisor * 16) + 10000;
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/* Spin */
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while (1)
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{
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uint64_t new_cycle;
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CVMX_MF_CYCLE (new_cycle);
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if (new_cycle >= read_cycle)
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break;
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}
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}
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/* Don't enable flow control until after baud rate is configured. - we don't want
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** to allow characters in until after the baud rate is fully configured */
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cvmx_write_csr(CVMX_MIO_UARTX_MCR(uart_index), mcrval.u64);
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return 0;
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}
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/**
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* Setup a uart for use
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*
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* @param uart_index Uart to setup (0 or 1)
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* @return Zero on success
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*/
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int cvmx_uart_setup (int uart_index)
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{
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return cvmx_uart_setup2(uart_index, cvmx_clock_get_rate (CVMX_CLOCK_SCLK), 115200);
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}
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