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8562ad200e
detection and remove the long delays that I had used previously. Everything should be handled by timeouts now.
596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Macronix register definitions.
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*/
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#define MX_BUSCTL 0x00 /* bus control */
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#define MX_TXSTART 0x08 /* tx start demand */
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#define MX_RXSTART 0x10 /* rx start demand */
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#define MX_RXADDR 0x18 /* rx descriptor list start addr */
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#define MX_TXADDR 0x20 /* tx descriptor list start addr */
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#define MX_ISR 0x28 /* interrupt status register */
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#define MX_NETCFG 0x30 /* network config register */
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#define MX_IMR 0x38 /* interrupt mask */
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#define MX_FRAMESDISCARDED 0x40 /* # of discarded frames */
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#define MX_SIO 0x48 /* MII and ROM/EEPROM access */
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#define MX_RESERVED 0x50
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#define MX_TIMER 0x58 /* general timer */
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#define MX_10BTSTAT 0x60
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#define MX_SIARESET 0x68
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#define MX_10BTCTRL 0x70
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#define MX_WATCHDOG 0x78
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#define MX_MAGICPACKET 0x80
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#define MX_NWAYSTAT 0xA0
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/*
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* These are magic values that must be written into CSR16
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* (MX_MAGICPACKET) in order to put the chip into proper
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* operating mode. The magic numbers are documented in the
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* Macronix 98715 application notes.
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*/
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#define MX_MAGIC_98713 0x0F370000
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#define MX_MAGIC_98713A 0x0B3C0000
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#define MX_MAGIC_98715 0x0B3C0000
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#define MX_MAGIC_98725 0x0B3C0000
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#define MX_REVISION_98713 0x00
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#define MX_REVISION_98713A 0x10
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#define MX_REVISION_98715 0x20
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#define MX_REVISION_98725 0x30
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/*
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* As far as the driver is concerned, there are two 'types' of
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* chips to be concerned with. One is a 98713 with an external
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* PHY on the MII. The other covers pretty much everything else,
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* since all the other Macronix chips have built-in transceivers.
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* This type setting governs what which mode selection routines
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* we use (MII or built-in). It also govers which of the 'magic'
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* numbers we write into CSR16.
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*/
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#define MX_TYPE_98713 0x1
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#define MX_TYPE_98713A 0x2
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#define MX_TYPE_987x5 0x3
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/*
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* Bus control bits.
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*/
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#define MX_BUSCTL_RESET 0x00000001
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#define MX_BUSCTL_ARBITRATION 0x00000002
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#define MX_BUSCTL_SKIPLEN 0x0000007C
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#define MX_BUSCTL_BUF_BIGENDIAN 0x00000080
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#define MX_BUSCTL_BURSTLEN 0x00003F00
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#define MX_BUSCTL_CACHEALIGN 0x0000C000
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#define MX_BUSCTL_TXPOLL 0x000E0000
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#define MX_BUSCTL_MUSTBEONE 0x04000000
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#define MX_SKIPLEN_1LONG 0x00000004
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#define MX_SKIPLEN_2LONG 0x00000008
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#define MX_SKIPLEN_3LONG 0x00000010
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#define MX_SKIPLEN_4LONG 0x00000020
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#define MX_SKIPLEN_5LONG 0x00000040
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#define MX_CACHEALIGN_NONE 0x00000000
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#define MX_CACHEALIGN_8LONG 0x00004000
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#define MX_CACHEALIGN_16LONG 0x00008000
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#define MX_CACHEALIGN_32LONG 0x0000C000
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#define MX_BURSTLEN_USECA 0x00000000
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#define MX_BURSTLEN_1LONG 0x00000100
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#define MX_BURSTLEN_2LONG 0x00000200
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#define MX_BURSTLEN_4LONG 0x00000400
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#define MX_BURSTLEN_8LONG 0x00000800
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#define MX_BURSTLEN_16LONG 0x00001000
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#define MX_BURSTLEN_32LONG 0x00002000
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#define MX_TXPOLL_OFF 0x00000000
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#define MX_TXPOLL_200U 0x00020000
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#define MX_TXPOLL_800U 0x00040000
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#define MX_TXPOLL_1600U 0x00060000
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#define MX_BUSCTL_CONFIG (MX_BUSCTL_ARBITRATION|MX_CACHEALIGN_8LONG| \
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MX_BURSTLEN_8LONG)
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/*
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* Interrupt status bits.
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*/
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#define MX_ISR_TX_OK 0x00000001
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#define MX_ISR_TX_IDLE 0x00000002
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#define MX_ISR_TX_NOBUF 0x00000004
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#define MX_ISR_TX_JABBERTIMEO 0x00000008
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#define MX_ISR_LINKGOOD 0x00000010
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#define MX_ISR_TX_UNDERRUN 0x00000020
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#define MX_ISR_RX_OK 0x00000040
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#define MX_ISR_RX_NOBUF 0x00000080
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#define MX_ISR_RX_READ 0x00000100
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#define MX_ISR_RX_WATDOGTIMEO 0x00000200
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#define MX_ISR_TX_EARLY 0x00000400
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#define MX_ISR_TIMER_EXPIRED 0x00000800
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#define MX_ISR_LINKFAIL 0x00001000
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#define MX_ISR_BUS_ERR 0x00002000
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#define MX_ISR_RX_EARLY 0x00004000
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#define MX_ISR_ABNORMAL 0x00008000
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#define MX_ISR_NORMAL 0x00010000
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#define MX_ISR_RX_STATE 0x000E0000
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#define MX_ISR_TX_STATE 0x00700000
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#define MX_ISR_BUSERRTYPE 0x03800000
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#define MX_ISR_100MBPSLINK 0x08000000
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#define MX_ISR_MAGICKPACK 0x10000000
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#define MX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
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#define MX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
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#define MX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
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#define MX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
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#define MX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
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#define MX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
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#define MX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
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#define MX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
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#define MX_TXSTATE_RESET 0x00000000 /* 000 - reset */
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#define MX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
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#define MX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
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#define MX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
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#define MX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
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#define MX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
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#define MX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
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#define MX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
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/*
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* Network config bits.
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*/
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#define MX_NETCFG_RX_HASHPERF 0x00000001
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#define MX_NETCFG_RX_ON 0x00000002
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#define MX_NETCFG_RX_HASHONLY 0x00000004
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#define MX_NETCFG_RX_BADFRAMES 0x00000008
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#define MX_NETCFG_RX_INVFILT 0x00000010
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#define MX_NETCFG_BACKOFFCNT 0x00000020
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#define MX_NETCFG_RX_PROMISC 0x00000040
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#define MX_NETCFG_RX_ALLMULTI 0x00000080
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#define MX_NETCFG_FULLDUPLEX 0x00000200
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#define MX_NETCFG_LOOPBACK 0x00000C00
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#define MX_NETCFG_FORCECOLL 0x00001000
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#define MX_NETCFG_TX_ON 0x00002000
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#define MX_NETCFG_TX_THRESH 0x0000C000
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#define MX_NETCFG_TX_BACKOFF 0x00020000
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#define MX_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
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#define MX_NETCFG_HEARTBEAT 0x00080000
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#define MX_NETCFG_STORENFWD 0x00200000
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#define MX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
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#define MX_NETCFG_PCS 0x00800000
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#define MX_NETCFG_SCRAMBLER 0x01000000
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#define MX_NETCFG_NO_RXCRC 0x02000000
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#define MX_OPMODE_NORM 0x00000000
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#define MX_OPMODE_INTLOOP 0x00000400
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#define MX_OPMODE_EXTLOOP 0x00000800
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#define MX_TXTHRESH_72BYTES 0x00000000
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#define MX_TXTHRESH_96BYTES 0x00004000
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#define MX_TXTHRESH_128BYTES 0x00008000
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#define MX_TXTHRESH_160BYTES 0x0000C000
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/*
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* Interrupt mask bits.
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*/
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#define MX_IMR_TX_OK 0x00000001
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#define MX_IMR_TX_IDLE 0x00000002
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#define MX_IMR_TX_NOBUF 0x00000004
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#define MX_IMR_TX_JABBERTIMEO 0x00000008
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#define MX_IMR_LINKGOOD 0x00000010
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#define MX_IMR_TX_UNDERRUN 0x00000020
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#define MX_IMR_RX_OK 0x00000040
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#define MX_IMR_RX_NOBUF 0x00000080
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#define MX_IMR_RX_READ 0x00000100
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#define MX_IMR_RX_WATDOGTIMEO 0x00000200
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#define MX_IMR_TX_EARLY 0x00000400
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#define MX_IMR_TIMER_EXPIRED 0x00000800
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#define MX_IMR_LINKFAIL 0x00001000
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#define MX_IMR_BUS_ERR 0x00002000
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#define MX_IMR_RX_EARLY 0x00004000
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#define MX_IMR_ABNORMAL 0x00008000
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#define MX_IMR_NORMAL 0x00010000
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#define MX_IMR_100MBPSLINK 0x08000000
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#define MX_IMR_MAGICKPACK 0x10000000
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#define MX_INTRS \
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(MX_IMR_RX_OK|MX_IMR_TX_OK|MX_IMR_RX_NOBUF|MX_IMR_RX_WATDOGTIMEO|\
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MX_IMR_TX_NOBUF|MX_IMR_TX_UNDERRUN|MX_IMR_BUS_ERR| \
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MX_IMR_ABNORMAL|MX_IMR_NORMAL/*|MX_IMR_TX_EARLY*/)
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/*
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* Serial I/O (EEPROM/ROM) bits.
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*/
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#define MX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
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#define MX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
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#define MX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
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#define MX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
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#define MX_SIO_ROMDATA4 0x00000010
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#define MX_SIO_ROMDATA5 0x00000020
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#define MX_SIO_ROMDATA6 0x00000040
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#define MX_SIO_ROMDATA7 0x00000080
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#define MX_SIO_EESEL 0x00000800
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#define MX_SIO_ROMSEL 0x00001000
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#define MX_SIO_ROMCTL_WRITE 0x00002000
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#define MX_SIO_ROMCTL_READ 0x00004000
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#define MX_SIO_MII_CLK 0x00010000 /* MDIO clock */
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#define MX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
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#define MX_SIO_MII_DIR 0x00040000 /* MDIO dir */
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#define MX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
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#define MX_EECMD_WRITE 0x140
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#define MX_EECMD_READ 0x180
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#define MX_EECMD_ERASE 0x1c0
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#define MX_EE_NODEADDR_OFFSET 0x70
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#define MX_EE_NODEADDR 10
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/*
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* General purpose timer register
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*/
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#define MX_TIMER_VALUE 0x0000FFFF
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#define MX_TIMER_CONTINUUS 0x00010000
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/*
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* 10baseT status register
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*/
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#define MX_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
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#define MX_TSTAT_LS10 0x00000004 /* link status of 10baseT */
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#define MX_TSTAT_AUTOPOLARITY 0x00000008
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#define MX_TSTAT_REMFAULT 0x00000800
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#define MX_TSTAT_ANEGSTAT 0x00007000
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#define MX_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
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#define MX_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
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#define MX_ASTAT_DISABLE 0x00000000
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#define MX_ASTAT_TXDISABLE 0x00001000
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#define MX_ASTAT_ABDETECT 0x00002000
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#define MX_ASTAT_ACKDETECT 0x00003000
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#define MX_ASTAT_CMPACKDETECT 0x00004000
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#define MX_ASTAT_AUTONEGCMP 0x00005000
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#define MX_ASTAT_LINKCHECK 0x00006000
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/*
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* PHY reset register
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*/
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#define MX_SIA_RESET_NWAY 0x00000001
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#define MX_SIA_RESET_100TX 0x00000002
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/*
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* 10baseT control register
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*/
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#define MX_TCTL_LOOPBACK 0x00000002
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#define MX_TCTL_POWERDOWN 0x00000004
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#define MX_TCTL_HALFDUPLEX 0x00000040
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#define MX_TCTL_AUTONEGENBL 0x00000080
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#define MX_TCTL_RX_SQUELCH 0x00000100
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#define MX_TCTL_LINKTEST 0x00001000
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#define MX_TCTL_100BTXHALF 0x00010000
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#define MX_TCTL_100BTXFULL 0x00020000
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#define MX_TCTL_100BT4 0x00040000
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/*
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* Watchdog timer register
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*/
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#define MX_WDOG_JABBERDIS 0x00000001
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#define MX_WDOG_HOSTUNJAB 0x00000002
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#define MX_WDOG_JABBERCLK 0x00000004
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#define MX_WDOG_RXWDOGDIS 0x00000010
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#define MX_WDOG_RXWDOGCLK 0x00000020
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#define MX_WDOG_MUSTBEZERO 0x00000100
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/*
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* Magic packet register
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*/
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#define MX_MPACK_DISABLE 0x00400000
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/*
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* NWAY status register.
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*/
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#define MX_NWAY_10BTHALF 0x08000000
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#define MX_NWAY_10BTFULL 0x10000000
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#define MX_NWAY_100BTHALF 0x20000000
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#define MX_NWAY_100BTFULL 0x40000000
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#define MX_NWAY_100BT4 0x80000000
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/*
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* Size of a setup frame.
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*/
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#define MX_SFRAME_LEN 192
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/*
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* Macronix TX/RX list structure.
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*/
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struct mx_desc {
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u_int32_t mx_status;
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u_int32_t mx_ctl;
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u_int32_t mx_ptr1;
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u_int32_t mx_ptr2;
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};
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#define mx_data mx_ptr1
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#define mx_next mx_ptr2
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#define MX_RXSTAT_FIFOOFLOW 0x00000001
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#define MX_RXSTAT_CRCERR 0x00000002
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#define MX_RXSTAT_DRIBBLE 0x00000004
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#define MX_RXSTAT_WATCHDOG 0x00000010
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#define MX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
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#define MX_RXSTAT_COLLSEEN 0x00000040
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#define MX_RXSTAT_GIANT 0x00000080
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#define MX_RXSTAT_LASTFRAG 0x00000100
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#define MX_RXSTAT_FIRSTFRAG 0x00000200
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#define MX_RXSTAT_MULTICAST 0x00000400
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#define MX_RXSTAT_RUNT 0x00000800
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#define MX_RXSTAT_RXTYPE 0x00003000
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#define MX_RXSTAT_RXERR 0x00008000
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#define MX_RXSTAT_RXLEN 0x3FFF0000
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#define MX_RXSTAT_OWN 0x80000000
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#define MX_RXBYTES(x) ((x & MX_RXSTAT_RXLEN) >> 16)
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#define MX_RXSTAT (MX_RXSTAT_FIRSTFRAG|MX_RXSTAT_LASTFRAG|MX_RXSTAT_OWN)
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#define MX_RXCTL_BUFLEN1 0x00000FFF
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#define MX_RXCTL_BUFLEN2 0x00FFF000
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#define MX_RXCTL_RLINK 0x01000000
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#define MX_RXCTL_RLAST 0x02000000
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#define MX_TXSTAT_DEFER 0x00000001
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#define MX_TXSTAT_UNDERRUN 0x00000002
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#define MX_TXSTAT_LINKFAIl 0x00000003
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#define MX_TXSTAT_COLLCNT 0x00000078
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#define MX_TXSTAT_SQE 0x00000080
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#define MX_TXSTAT_EXCESSCOLL 0x00000100
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#define MX_TXSTAT_LATECOLL 0x00000200
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#define MX_TXSTAT_NOCARRIER 0x00000400
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#define MX_TXSTAT_CARRLOST 0x00000800
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#define MX_TXSTAT_JABTIMEO 0x00004000
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#define MX_TXSTAT_ERRSUM 0x00008000
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#define MX_TXSTAT_OWN 0x80000000
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#define MX_TXCTL_BUFLEN1 0x000007FF
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#define MX_TXCTL_BUFLEN2 0x003FF800
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#define MX_TXCTL_FILTTYPE0 0x00400000
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#define MX_TXCTL_PAD 0x00800000
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#define MX_TXCTL_TLINK 0x01000000
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#define MX_TXCTL_TLAST 0x02000000
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#define MX_TXCTL_NOCRC 0x04000000
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#define MX_TXCTL_SETUP 0x08000000
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#define MX_TXCTL_FILTTYPE1 0x10000000
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#define MX_TXCTL_FIRSTFRAG 0x20000000
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#define MX_TXCTL_LASTFRAG 0x40000000
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#define MX_TXCTL_FINT 0x80000000
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#define MX_FILTER_PERFECT 0x00000000
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#define MX_FILTER_HASHPERF 0x00400000
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#define MX_FILTER_INVERSE 0x10000000
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#define MX_FILTER_HASHONLY 0x10400000
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#define MX_MAXFRAGS 16
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#define MX_RX_LIST_CNT 64
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#define MX_TX_LIST_CNT 128
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#define MX_MIN_FRAMELEN 60
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/*
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* A tx 'super descriptor' is actually 16 regular descriptors
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* back to back.
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*/
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struct mx_txdesc {
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struct mx_desc mx_frag[MX_MAXFRAGS];
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};
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#define MX_TXNEXT(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_next
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#define MX_TXSTATUS(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_status
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#define MX_TXCTL(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_ctl
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#define MX_TXDATA(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_data
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#define MX_TXOWN(x) x->mx_ptr->mx_frag[0].mx_status
|
|
|
|
struct mx_list_data {
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|
struct mx_desc mx_rx_list[MX_RX_LIST_CNT];
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|
struct mx_txdesc mx_tx_list[MX_TX_LIST_CNT];
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|
};
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|
|
|
struct mx_chain {
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|
struct mx_txdesc *mx_ptr;
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|
struct mbuf *mx_mbuf;
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|
struct mx_chain *mx_nextdesc;
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|
u_int8_t mx_lastdesc;
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|
};
|
|
|
|
struct mx_chain_onefrag {
|
|
struct mx_desc *mx_ptr;
|
|
struct mbuf *mx_mbuf;
|
|
struct mx_chain_onefrag *mx_nextdesc;
|
|
};
|
|
|
|
struct mx_chain_data {
|
|
struct mx_desc mx_sframe;
|
|
u_int32_t mx_sbuf[MX_SFRAME_LEN/sizeof(u_int32_t)];
|
|
u_int8_t mx_pad[MX_MIN_FRAMELEN];
|
|
struct mx_chain_onefrag mx_rx_chain[MX_RX_LIST_CNT];
|
|
struct mx_chain mx_tx_chain[MX_TX_LIST_CNT];
|
|
|
|
struct mx_chain_onefrag *mx_rx_head;
|
|
|
|
struct mx_chain *mx_tx_head;
|
|
struct mx_chain *mx_tx_tail;
|
|
struct mx_chain *mx_tx_free;
|
|
};
|
|
|
|
struct mx_type {
|
|
u_int16_t mx_vid;
|
|
u_int16_t mx_did;
|
|
char *mx_name;
|
|
};
|
|
|
|
struct mx_mii_frame {
|
|
u_int8_t mii_stdelim;
|
|
u_int8_t mii_opcode;
|
|
u_int8_t mii_phyaddr;
|
|
u_int8_t mii_regaddr;
|
|
u_int8_t mii_turnaround;
|
|
u_int16_t mii_data;
|
|
};
|
|
|
|
/*
|
|
* MII constants
|
|
*/
|
|
#define MX_MII_STARTDELIM 0x01
|
|
#define MX_MII_READOP 0x02
|
|
#define MX_MII_WRITEOP 0x01
|
|
#define MX_MII_TURNAROUND 0x02
|
|
|
|
#define MX_FLAG_FORCEDELAY 1
|
|
#define MX_FLAG_SCHEDDELAY 2
|
|
#define MX_FLAG_DELAYTIMEO 3
|
|
|
|
struct mx_softc {
|
|
struct arpcom arpcom; /* interface info */
|
|
bus_space_handle_t mx_bhandle; /* bus space handle */
|
|
bus_space_tag_t mx_btag; /* bus space tag */
|
|
void *mx_intrhand;
|
|
struct resource *mx_irq;
|
|
struct resource *mx_res;
|
|
device_t mx_miibus;
|
|
struct mx_type *mx_info; /* Macronix adapter info */
|
|
u_int8_t mx_unit; /* interface number */
|
|
u_int8_t mx_type;
|
|
u_int8_t mx_cachesize;
|
|
u_int8_t mx_link;
|
|
int mx_if_flags;
|
|
caddr_t mx_ldata_ptr;
|
|
struct mx_list_data *mx_ldata;
|
|
struct mx_chain_data mx_cdata;
|
|
struct callout_handle mx_stat_ch;
|
|
};
|
|
|
|
/*
|
|
* register space access macros
|
|
*/
|
|
#define CSR_WRITE_4(sc, reg, val) \
|
|
bus_space_write_4(sc->mx_btag, sc->mx_bhandle, reg, val)
|
|
#define CSR_WRITE_2(sc, reg, val) \
|
|
bus_space_write_2(sc->mx_btag, sc->mx_bhandle, reg, val)
|
|
#define CSR_WRITE_1(sc, reg, val) \
|
|
bus_space_write_1(sc->mx_btag, sc->mx_bhandle, reg, val)
|
|
|
|
#define CSR_READ_4(sc, reg) \
|
|
bus_space_read_4(sc->mx_btag, sc->mx_bhandle, reg)
|
|
#define CSR_READ_2(sc, reg) \
|
|
bus_space_read_2(sc->mx_btag, sc->mx_bhandle, reg)
|
|
#define CSR_READ_1(sc, reg) \
|
|
bus_space_read_1(sc->mx_btag, sc->mx_bhandle, reg)
|
|
|
|
#define MX_TIMEOUT 1000
|
|
#define ETHER_ALIGN 2
|
|
|
|
/*
|
|
* General constants that are fun to know.
|
|
*
|
|
* Macronix PCI vendor ID
|
|
*/
|
|
#define MX_VENDORID 0x10D9
|
|
|
|
/*
|
|
* Macronix PMAC device IDs.
|
|
*/
|
|
#define MX_DEVICEID_98713 0x0512
|
|
#define MX_DEVICEID_987x5 0x0531
|
|
|
|
/*
|
|
* Compex PCI vendor ID.
|
|
*/
|
|
#define CP_VENDORID 0x11F6
|
|
|
|
/*
|
|
* Compex PMAC PCI device IDs.
|
|
*/
|
|
#define CP_DEVICEID_98713 0x9881
|
|
|
|
/*
|
|
* Lite-On PNIC PCI vendor ID
|
|
*/
|
|
#define PN_VENDORID 0x11AD
|
|
|
|
/*
|
|
* Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
|
|
* with wake on lan/magic packet support.
|
|
*/
|
|
#define PN_DEVICEID_PNIC_II 0xc115
|
|
|
|
/*
|
|
* PCI low memory base and low I/O base register, and
|
|
* other PCI registers.
|
|
*/
|
|
|
|
#define MX_PCI_VENDOR_ID 0x00
|
|
#define MX_PCI_DEVICE_ID 0x02
|
|
#define MX_PCI_COMMAND 0x04
|
|
#define MX_PCI_STATUS 0x06
|
|
#define MX_PCI_REVID 0x08
|
|
#define MX_PCI_CLASSCODE 0x09
|
|
#define MX_PCI_CACHELEN 0x0C
|
|
#define MX_PCI_LATENCY_TIMER 0x0D
|
|
#define MX_PCI_HEADER_TYPE 0x0E
|
|
#define MX_PCI_LOIO 0x10
|
|
#define MX_PCI_LOMEM 0x14
|
|
#define MX_PCI_BIOSROM 0x30
|
|
#define MX_PCI_INTLINE 0x3C
|
|
#define MX_PCI_INTPIN 0x3D
|
|
#define MX_PCI_MINGNT 0x3E
|
|
#define MX_PCI_MINLAT 0x0F
|
|
#define MX_PCI_RESETOPT 0x48
|
|
#define MX_PCI_EEPROM_DATA 0x4C
|
|
|
|
/* power management registers */
|
|
#define MX_PCI_CAPID 0x44 /* 8 bits */
|
|
#define MX_PCI_NEXTPTR 0x45 /* 8 bits */
|
|
#define MX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
|
|
#define MX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
|
|
|
|
#define MX_PSTATE_MASK 0x0003
|
|
#define MX_PSTATE_D0 0x0000
|
|
#define MX_PSTATE_D1 0x0001
|
|
#define MX_PSTATE_D2 0x0002
|
|
#define MX_PSTATE_D3 0x0003
|
|
#define MX_PME_EN 0x0010
|
|
#define MX_PME_STATUS 0x8000
|
|
|
|
#ifdef __alpha__
|
|
#undef vtophys
|
|
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
|
#endif
|