Conrad Meyer e7f64f2e33 ntb: Add MW tunable for MMR Xeon errata workaround ... Adds a new tunable, ntb.hw.b2b_mw_idx, which specifies the offset (from the total number of memory windows) to use for register access on hardware with the SDOORBELL_LOCKUP errata. The default is -1, i.e., the last memory window. We map BARs before the b2b_mw_idx is selected, so map them all as memory windows initially. The register memory window should not be write-combined, so we explicitly disable WC on the selected MW later. This introduces a layer of abstraction between consumer memory window indices, which exclude any exclusive errata-workaround BARs, and internal memory window indices, which include such BARs. An internal routine, ntb_user_mw_to_idx(), converts the former to the latter. Public APIs have been updated to use this instead of assuming the exclusive workaround BAR is the last available MW. Sponsored by: EMC / Isilon Storage Division		2015-11-24 18:51:17 +00:00
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if_ntb	if_ntb: Initialize if_mtu to the correct MTU	2015-11-19 19:53:19 +00:00
ntb_hw	ntb: Add MW tunable for MMR Xeon errata workaround	2015-11-24 18:51:17 +00:00