Konstantin Belousov e164cafc69 Add hw.dmar.batch_coalesce tunable/sysctl, which specifies rate at ... which queued invalidation completion interrupt is requested with regard to the queued invalidation requests. In other words, setting the value of the knob to N requests completion interrupt after N items are processed. Existing behaviour is restored by setting hw.dmar.batch_coalesce=1. The knob significantly decreases the DMAR qi interrupt rate at the cost of slightly longer DMAR map entries recycling. Sponsored by: The FreeBSD Foundation		2016-04-17 10:56:56 +00:00
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busdma_dmar.c
busdma_dmar.h
intel_ctx.c	Add hw.dmar.batch_coalesce tunable/sysctl, which specifies rate at	2016-04-17 10:56:56 +00:00
intel_dmar.h	Add hw.dmar.batch_coalesce tunable/sysctl, which specifies rate at	2016-04-17 10:56:56 +00:00
intel_drv.c	Some BIOSes ACPI bytecode needs to take (sleepable) acpi mutex for	2016-02-20 13:37:04 +00:00
intel_fault.c	Remove taskqueue_enqueue_fast().	2016-03-01 17:47:32 +00:00
intel_gas.c
intel_idpgtbl.c
intel_intrmap.c
intel_qi.c	Remove taskqueue_enqueue_fast().	2016-03-01 17:47:32 +00:00
intel_quirks.c
intel_reg.h
intel_utils.c	Add hw.dmar.batch_coalesce tunable/sysctl, which specifies rate at	2016-04-17 10:56:56 +00:00
iommu_intrmap.h