mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-21 11:13:30 +00:00
57 lines
2.4 KiB
C
57 lines
2.4 KiB
C
/*-
|
|
* Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
#ifndef _ISA_ISA_DMAREG_H_
|
|
#define _ISA_ISA_DMAREG_H_
|
|
|
|
#include <dev/ic/i8237.h>
|
|
|
|
#define IO_DMA1 0x00 /* 8237A DMA Controller #1 */
|
|
#define IO_DMA2 0xC0 /* 8237A DMA Controller #2 */
|
|
|
|
/*
|
|
* Register definitions for DMA controller 1 (channels 0..3):
|
|
*/
|
|
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
|
|
#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */
|
|
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
|
|
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
|
|
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
|
|
#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
|
|
|
|
/*
|
|
* Register definitions for DMA controller 2 (channels 4..7):
|
|
*/
|
|
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
|
|
#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
|
|
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
|
|
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
|
|
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
|
|
#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
|
|
|
|
#endif /* _ISA_ISA_DMAREG_H_ */
|