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311 lines
11 KiB
Groff
311 lines
11 KiB
Groff
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.\" ========================================================================
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.\"
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.IX Title "LLI 1"
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.TH LLI 1 "2012-04-05" "LLVM 3.1" "LLVM Command Guide"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.if n .ad l
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.nh
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.SH "NAME"
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lli \- directly execute programs from LLVM bitcode
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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\&\fBlli\fR [\fIoptions\fR] [\fIfilename\fR] [\fIprogram args\fR]
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.SH "DESCRIPTION"
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.IX Header "DESCRIPTION"
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\&\fBlli\fR directly executes programs in \s-1LLVM\s0 bitcode format. It takes a program
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in \s-1LLVM\s0 bitcode format and executes it using a just-in-time compiler, if one is
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available for the current architecture, or an interpreter. \fBlli\fR takes all of
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the same code generator options as llc, but they are only effective when
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\&\fBlli\fR is using the just-in-time compiler.
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.PP
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If \fIfilename\fR is not specified, then \fBlli\fR reads the \s-1LLVM\s0 bitcode for the
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program from standard input.
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.PP
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The optional \fIargs\fR specified on the command line are passed to the program as
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arguments.
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.SH "GENERAL OPTIONS"
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.IX Header "GENERAL OPTIONS"
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.IP "\fB\-fake\-argv0\fR=\fIexecutable\fR" 4
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.IX Item "-fake-argv0=executable"
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Override the \f(CW\*(C`argv[0]\*(C'\fR value passed into the executing program.
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.IP "\fB\-force\-interpreter\fR=\fI{false,true}\fR" 4
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.IX Item "-force-interpreter={false,true}"
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If set to true, use the interpreter even if a just-in-time compiler is available
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for this architecture. Defaults to false.
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.IP "\fB\-help\fR" 4
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.IX Item "-help"
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Print a summary of command line options.
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.IP "\fB\-load\fR=\fIpuginfilename\fR" 4
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.IX Item "-load=puginfilename"
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Causes \fBlli\fR to load the plugin (shared object) named \fIpluginfilename\fR and use
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it for optimization.
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.IP "\fB\-stats\fR" 4
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.IX Item "-stats"
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Print statistics from the code-generation passes. This is only meaningful for
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the just-in-time compiler, at present.
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.IP "\fB\-time\-passes\fR" 4
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.IX Item "-time-passes"
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Record the amount of time needed for each code-generation pass and print it to
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standard error.
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.IP "\fB\-version\fR" 4
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.IX Item "-version"
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Print out the version of \fBlli\fR and exit without doing anything else.
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.SH "TARGET OPTIONS"
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.IX Header "TARGET OPTIONS"
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.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4
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.IX Item "-mtriple=target triple"
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Override the target triple specified in the input bitcode file with the
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specified string. This may result in a crash if you pick an
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architecture which is not compatible with the current system.
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.IP "\fB\-march\fR=\fIarch\fR" 4
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.IX Item "-march=arch"
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Specify the architecture for which to generate assembly, overriding the target
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encoded in the bitcode file. See the output of \fBllc \-help\fR for a list of
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valid architectures. By default this is inferred from the target triple or
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autodetected to the current architecture.
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.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4
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.IX Item "-mcpu=cpuname"
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Specify a specific chip in the current architecture to generate code for.
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By default this is inferred from the target triple and autodetected to
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the current architecture. For a list of available CPUs, use:
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\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR
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.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4
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.IX Item "-mattr=a1,+a2,-a3,..."
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Override or control specific attributes of the target, such as whether \s-1SIMD\s0
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operations are enabled or not. The default set of attributes is set by the
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current \s-1CPU\s0. For a list of available attributes, use:
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\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR
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.SH "FLOATING POINT OPTIONS"
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.IX Header "FLOATING POINT OPTIONS"
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.IP "\fB\-disable\-excess\-fp\-precision\fR" 4
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.IX Item "-disable-excess-fp-precision"
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Disable optimizations that may increase floating point precision.
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.IP "\fB\-enable\-no\-infs\-fp\-math\fR" 4
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.IX Item "-enable-no-infs-fp-math"
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Enable optimizations that assume no Inf values.
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.IP "\fB\-enable\-no\-nans\-fp\-math\fR" 4
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.IX Item "-enable-no-nans-fp-math"
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Enable optimizations that assume no \s-1NAN\s0 values.
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.IP "\fB\-enable\-unsafe\-fp\-math\fR" 4
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.IX Item "-enable-unsafe-fp-math"
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Causes \fBlli\fR to enable optimizations that may decrease floating point
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precision.
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.IP "\fB\-soft\-float\fR" 4
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.IX Item "-soft-float"
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Causes \fBlli\fR to generate software floating point library calls instead of
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equivalent hardware instructions.
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.SH "CODE GENERATION OPTIONS"
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.IX Header "CODE GENERATION OPTIONS"
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.IP "\fB\-code\-model\fR=\fImodel\fR" 4
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.IX Item "-code-model=model"
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Choose the code model from:
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.Sp
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.Vb 5
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\& default: Target default code model
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\& small: Small code model
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\& kernel: Kernel code model
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\& medium: Medium code model
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\& large: Large code model
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.Ve
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.IP "\fB\-disable\-post\-RA\-scheduler\fR" 4
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.IX Item "-disable-post-RA-scheduler"
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Disable scheduling after register allocation.
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.IP "\fB\-disable\-spill\-fusing\fR" 4
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.IX Item "-disable-spill-fusing"
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Disable fusing of spill code into instructions.
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.IP "\fB\-enable\-correct\-eh\-support\fR" 4
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.IX Item "-enable-correct-eh-support"
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Make the \-lowerinvoke pass insert expensive, but correct, \s-1EH\s0 code.
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.IP "\fB\-jit\-enable\-eh\fR" 4
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.IX Item "-jit-enable-eh"
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Exception handling should be enabled in the just-in-time compiler.
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.IP "\fB\-join\-liveintervals\fR" 4
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.IX Item "-join-liveintervals"
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Coalesce copies (default=true).
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.IP "\fB\-nozero\-initialized\-in\-bss\fR Don't place zero-initialized symbols into the \s-1BSS\s0 section." 4
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.IX Item "-nozero-initialized-in-bss Don't place zero-initialized symbols into the BSS section."
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.PD 0
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.IP "\fB\-pre\-RA\-sched\fR=\fIscheduler\fR" 4
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.IX Item "-pre-RA-sched=scheduler"
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.PD
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Instruction schedulers available (before register allocation):
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.Sp
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.Vb 7
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\& =default: Best scheduler for the target
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\& =none: No scheduling: breadth first sequencing
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\& =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
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\& =simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency
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\& =list\-burr: Bottom\-up register reduction list scheduling
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\& =list\-tdrr: Top\-down register reduction list scheduling
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\& =list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code
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.Ve
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.IP "\fB\-regalloc\fR=\fIallocator\fR" 4
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.IX Item "-regalloc=allocator"
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Register allocator to use (default=linearscan)
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.Sp
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.Vb 3
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\& =bigblock: Big\-block register allocator
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\& =linearscan: linear scan register allocator =local \- local register allocator
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\& =simple: simple register allocator
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.Ve
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.IP "\fB\-relocation\-model\fR=\fImodel\fR" 4
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.IX Item "-relocation-model=model"
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Choose relocation model from:
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.Sp
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.Vb 3
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\& =default: Target default relocation model
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\& =static: Non\-relocatable code =pic \- Fully relocatable, position independent code
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\& =dynamic\-no\-pic: Relocatable external references, non\-relocatable code
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.Ve
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.IP "\fB\-spiller\fR" 4
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.IX Item "-spiller"
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Spiller to use (default=local)
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.Sp
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.Vb 2
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\& =simple: simple spiller
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\& =local: local spiller
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.Ve
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.IP "\fB\-x86\-asm\-syntax\fR=\fIsyntax\fR" 4
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.IX Item "-x86-asm-syntax=syntax"
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Choose style of code to emit from X86 backend:
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.Sp
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.Vb 2
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\& =att: Emit AT&T\-style assembly
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\& =intel: Emit Intel\-style assembly
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.Ve
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.SH "EXIT STATUS"
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.IX Header "EXIT STATUS"
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If \fBlli\fR fails to load the program, it will exit with an exit code of 1.
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Otherwise, it will return the exit code of the program it executes.
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.SH "SEE ALSO"
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.IX Header "SEE ALSO"
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llc
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.SH "AUTHOR"
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.IX Header "AUTHOR"
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Maintained by the \s-1LLVM\s0 Team (<http://llvm.org/>).
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