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194 lines
6.0 KiB
C
194 lines
6.0 KiB
C
/*
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* Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
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* Copyright (c) 2003 by Quinton Dolan <q@onthenet.com.au>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_nvreg.h,v 1.6 2004/08/12 14:00:05 q Exp $
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* $FreeBSD$
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*/
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#ifndef _IF_NVEREG_H_
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#define _IF_NVEREG_H_
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#ifndef PCI_VENDOR_NVIDIA
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#define PCI_VENDOR_NVIDIA 0x10DE
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#endif
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#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
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#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
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#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
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#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
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#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
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#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
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#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
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#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
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#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
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#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
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#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
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#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
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#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
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#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
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#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
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#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
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#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
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#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
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#define NV_RID 0x10
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#define TX_RING_SIZE 64
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#define RX_RING_SIZE 64
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#define NV_MAX_FRAGS 32 // match adapter.h:ADAPTER_WRITE_DATA.sElement[]
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#define FCS_LEN 4
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#define NVE_DEBUG 0x0000
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#define NVE_DEBUG_INIT 0x0001
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#define NVE_DEBUG_RUNNING 0x0002
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#define NVE_DEBUG_DEINIT 0x0004
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#define NVE_DEBUG_IOCTL 0x0008
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#define NVE_DEBUG_INTERRUPT 0x0010
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#define NVE_DEBUG_API 0x0020
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#define NVE_DEBUG_LOCK 0x0040
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#define NVE_DEBUG_BROKEN 0x0080
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#define NVE_DEBUG_MII 0x0100
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#define NVE_DEBUG_ALL 0xFFFF
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#if NVE_DEBUG
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#define DEBUGOUT(level, fmt, args...) if (NVE_DEBUG & level) \
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printf(fmt, ## args)
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#else
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#define DEBUGOUT(level, fmt, args...)
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#endif
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typedef unsigned long ulong;
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struct nve_map_buffer {
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struct mbuf *mbuf; /* mbuf receiving packet */
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bus_dmamap_t map; /* DMA map */
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};
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struct nve_dma_info {
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bus_dma_tag_t tag;
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struct nve_map_buffer buf;
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u_int16_t buflength;
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caddr_t vaddr; /* Virtual memory address */
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bus_addr_t paddr; /* DMA physical address */
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};
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struct nve_rx_desc {
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struct nve_rx_desc *next;
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struct nve_map_buffer buf;
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u_int16_t buflength;
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caddr_t vaddr;
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bus_addr_t paddr;
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};
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struct nve_tx_desc {
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/* Don't add anything above this structure */
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TX_INFO_ADAP TxInfoAdap;
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struct nve_tx_desc *next;
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struct nve_map_buffer buf;
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u_int16_t buflength;
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u_int32_t numfrags;
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bus_dma_segment_t frags[NV_MAX_FRAGS];
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};
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struct nve_softc {
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struct ifnet *ifp; /* interface info */
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struct resource *res;
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struct resource *irq;
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ADAPTER_API *hwapi;
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OS_API osapi;
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device_t miibus;
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device_t dev;
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struct callout stat_callout;
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int tx_timer;
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void *sc_ih;
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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bus_dma_tag_t mtag;
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bus_dma_tag_t rtag;
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bus_dmamap_t rmap;
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bus_dma_tag_t ttag;
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bus_dmamap_t tmap;
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struct nve_rx_desc *rx_desc;
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struct nve_tx_desc *tx_desc;
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bus_addr_t rx_addr;
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bus_addr_t tx_addr;
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u_int16_t rx_ring_full;
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u_int16_t tx_ring_full;
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u_int32_t cur_rx;
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u_int32_t cur_tx;
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u_int32_t pending_rxs;
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u_int32_t pending_txs;
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struct mtx mtx;
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/* Stuff for dealing with the NVIDIA OS API */
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struct callout ostimer;
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PTIMER_FUNC ostimer_func;
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void *ostimer_params;
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int linkup;
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ulong tx_errors;
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NV_UINT32 hwmode;
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NV_UINT32 max_frame_size;
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NV_UINT32 phyaddr;
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NV_UINT32 media;
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CMNDATA_OS_ADAPTER adapterdata;
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unsigned char original_mac_addr[6];
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};
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struct nve_type {
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u_int16_t vid_id;
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u_int16_t dev_id;
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char *name;
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};
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#define NVE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define NVE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define NVE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
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extern int ADAPTER_ReadPhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG *pulVal);
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extern int ADAPTER_WritePhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG ulVal);
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extern int ADAPTER_Init (PVOID pContext, USHORT usForcedSpeed, UCHAR ucForceDpx, UCHAR ucForceMode, UINT *puiLinkState);
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#endif /* _IF_NVEREG_H_ */
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