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56a7c4a852
ahc_pci.c: Add detach support. Make use of soft allocated on our behalf by newbus. For PCI devices, disable the mapping type we aren't using for extra protection from rogue code. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Sync perforce IDs. aic7xxx_freebsd.c: Capture the eventhandle returned by EVENTHANDER_REGISTER so we can kill the handler off during detach. Use AHC_* constants instead of hard coded numbers in a few more places. Test PPR option state when deciding to "really" negotiate when the CAM_NEGOTIATE flag is passed in a CCB. Make use of core "ahc_pause_and_flushwork" routine in our timeout handler rather than re-inventing this code. Cleanup all of our resources (really!) in ahc_platform_free(). We should be all set to become a module now. Implement the core ahc_detach() routine shared by all of the FreeBSD front-ends. aic7xxx_freebsd.h: Softc storage for our event handler. Null implementation for the ahc_platform_flushwork() OSM callback. FreeBSD doesn't need this as XPT callbacks are safe from all contexts and are done directly in ahc_done(). aic7xxx_inline.h: Implement new lazy interrupt scheme. To avoid an extra PCI bus read, we first check our completion queues to see if any work has completed. If work is available, we assume that this is the source of the interrupt and skip reading INTSTAT. Any remaining interrupt status will be cleared by a second call to the interrupt handler should the interrupt line still be asserted. This drops the interrupt handler down to a single PCI bus read in the common case of I/O completion. This is the same overhead as in the not so distant past, but the extra sanity of perforning a PCI read after clearing the command complete interrupt and before running the completion queue to avoid missing command complete interrupts added a cycle. aic7xxx.c: During initialization, be sure to initialize all scratch ram locations before they are read to avoid parity errors. In this case, we use a new function, ahc_unbusy_tcl() to initialize the scratch ram busy target table. Replace instances of ahc_index_busy_tcl() used to unbusy a tcl without looking at the old value with ahc_unbusy_tcl(). Modify ahc_sent_msg so that it can find single byte messages. ahc_sent_msg is now used to determine if a transfer negotiation attempt resulted in a bus free. Be more careful in filtering out only the SCSI interrupts of interest in ahc_handle_scsiint. Rearrange interrupt clearing code to ensure that at least one PCI transaction occurrs after hitting CLRSINT1 and writting to CLRINT. CLRSINT1 writes take a bit to take effect, and the re-arrangement provides sufficient delay to ensure the write to CLRINT is effective. The old code might report a spurious interrupt on some "fast" chipsets. export ahc-update_target_msg_request for use by OSM code. If a target does not respond to our ATN request, clear it once we move to a non-message phase. This avoids sending a MSG_NOOP in some later message out phase. Use max lun and max target constants instead of hard-coded values. Use softc storage built into our device_t under FreeBSD. Fix a bug in ahc_free() that caused us to delete resources that were not allocated. Clean up any tstate/lstate info in ahc_free(). Clear the powerdown state in ahc_reset() so that registers can be accessed. Add a preliminary function for pausing the chip and processing any posted work. Add a preliminary suspend and resume functions. aic7xxx.h: Limit the number of supported luns to 64. We don't support information unit transfers, so this is the maximum that makes sense for these chips. Add a new flag AHC_ALL_INTERRUPTS that forces the processing of all interrupt state in a single invokation of ahc_intr(). When the flag is not set, we use the lazy interrupt handling scheme. Add data structures to store controller state while we are suspended. Use constants instead of hard coded values where appropriate. Correct some harmless "unsigned/signed" conflicts. aic7xxx.seq: Only perform the SCSIBUSL fix on ULTRA2 or newer controllers. Older controllers seem to be confused by this. In target mode, ignore PHASEMIS during data phases. This bit seems to be flakey on U160 controllers acting in target mode. aic7xxx_pci.c: Add support for the 29160C CPCI adapter. Add definitions for subvendor ID information available for devices with the "9005" vendor id. We currently use this information to determine if a multi-function device doesn't have the second channel hooked up on a board. Add rudimentary power mode code so we can put the controller into the D0 state. In the future this will be an OSM callback so that in FreeBSD we don't duplicate functionality provided by the PCI code. The powerstate code was added after I'd completed my regression tests on this code. Only capture "left over BIOS state" if the POWRDN setting is not set in HCNTRL. In target mode, don't bother sending incremental CRC data.
93 lines
3.0 KiB
C
93 lines
3.0 KiB
C
/*
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* Interface to the 93C46/56 serial EEPROM that is used to store BIOS
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* settings for the aic7xxx based adaptec SCSI controllers. It can
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* also be used for 93C26 and 93C06 serial EEPROMS.
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*
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* Copyright (c) 1994, 1995, 2000 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/src/aic7xxx/aic7xxx_93cx6.h#5 $
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*
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* $FreeBSD$
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*/
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#ifndef _AIC7XXX_93CX6_H_
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#define _AIC7XXX_93CX6_H_
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typedef enum {
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C46 = 6,
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C56_66 = 8
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} seeprom_chip_t;
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struct seeprom_descriptor {
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struct ahc_softc *sd_ahc;
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u_int sd_control_offset;
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u_int sd_status_offset;
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u_int sd_dataout_offset;
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seeprom_chip_t sd_chip;
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uint16_t sd_MS;
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uint16_t sd_RDY;
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uint16_t sd_CS;
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uint16_t sd_CK;
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uint16_t sd_DO;
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uint16_t sd_DI;
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};
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/*
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* This function will read count 16-bit words from the serial EEPROM and
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* return their value in buf. The port address of the aic7xxx serial EEPROM
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* control register is passed in as offset. The following parameters are
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* also passed in:
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*
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* CS - Chip select
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* CK - Clock
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* DO - Data out
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* DI - Data in
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* RDY - SEEPROM ready
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* MS - Memory port mode select
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*
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* A failed read attempt returns 0, and a successful read returns 1.
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*/
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#define SEEPROM_INB(sd) \
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ahc_inb(sd->sd_ahc, sd->sd_control_offset)
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#define SEEPROM_OUTB(sd, value) \
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do { \
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ahc_outb(sd->sd_ahc, sd->sd_control_offset, value); \
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ahc_flush_device_writes(sd->sd_ahc); \
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} while(0)
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#define SEEPROM_STATUS_INB(sd) \
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ahc_inb(sd->sd_ahc, sd->sd_status_offset)
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#define SEEPROM_DATA_INB(sd) \
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ahc_inb(sd->sd_ahc, sd->sd_dataout_offset)
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int read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
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u_int start_addr, u_int count);
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int verify_cksum(struct seeprom_config *sc);
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#endif /* _AIC7XXX_93CX6_H_ */
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