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9c03c0d88c
* On 32 bit platforms we steal the upper 4 bits of the map handle to store a unique map id. * On 64 bit platforms we steal the upper 24 bits. Resolves issues where the offsets that are handed to mmap may overlap the VRAM on some cards. Tested on: radeon, intel, mga, and via. This will break nouveau. I will spin new patches shortly.
1043 lines
27 KiB
C
1043 lines
27 KiB
C
/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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/*-
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "dev/drm/drmP.h"
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#include "dev/drm/drm.h"
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#include "dev/drm/i915_drm.h"
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#include "dev/drm/i915_drv.h"
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/* Really want an OS-independent resettable timer. Would like to have
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* this loop run for (eg) 3 sec, but have the timer reset every time
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* the head pointer changes, so that EBUSY only happens if the ring
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* actually stalls for (eg) 3 seconds.
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*/
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int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
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u32 last_acthd = I915_READ(acthd_reg);
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u32 acthd;
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int i;
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for (i = 0; i < 100000; i++) {
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ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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acthd = I915_READ(acthd_reg);
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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if (ring->space >= n)
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return 0;
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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if (ring->head != last_head)
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i = 0;
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if (acthd != last_acthd)
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i = 0;
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last_head = ring->head;
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last_acthd = acthd;
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DRM_UDELAY(10 * 1000);
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}
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return -EBUSY;
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}
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/**
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* Sets up the hardware status page for devices that need a physical address
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* in the register.
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*/
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static int i915_init_phys_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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/* Program Hardware Status Page */
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DRM_UNLOCK();
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dev_priv->status_page_dmah =
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drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
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DRM_LOCK();
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if (!dev_priv->status_page_dmah) {
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DRM_ERROR("Can not allocate hardware status page\n");
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return -ENOMEM;
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}
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dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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DRM_DEBUG("Enabled hardware status page\n");
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return 0;
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}
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/**
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* Frees the hardware status page, whether it's a physical address or a virtual
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* address set up by the X Server.
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*/
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static void i915_free_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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if (dev_priv->status_page_dmah) {
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drm_pci_free(dev, dev_priv->status_page_dmah);
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dev_priv->status_page_dmah = NULL;
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}
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if (dev_priv->status_gfx_addr) {
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dev_priv->status_gfx_addr = 0;
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drm_core_ioremapfree(&dev_priv->hws_map, dev);
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}
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/* Need to rewrite hardware status page */
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I915_WRITE(HWS_PGA, 0x1ffff000);
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}
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void i915_kernel_lost_context(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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if (ring->head == ring->tail && dev_priv->sarea_priv)
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}
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static int i915_dma_cleanup(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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/* Make sure interrupts are disabled here because the uninstall ioctl
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* may not have been called from userspace and after dev_private
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* is freed, it's too late.
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*/
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if (dev->irq_enabled)
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drm_irq_uninstall(dev);
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if (dev_priv->ring.virtual_start) {
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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dev_priv->ring.virtual_start = NULL;
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dev_priv->ring.map.virtual = NULL;
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dev_priv->ring.map.size = 0;
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}
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/* Clear the HWS virtual address at teardown */
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if (I915_NEED_GFX_HWS(dev))
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i915_free_hws(dev);
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return 0;
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}
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static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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dev_priv->sarea = drm_getsarea(dev);
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if (!dev_priv->sarea) {
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DRM_ERROR("can not find sarea!\n");
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i915_dma_cleanup(dev);
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return -EINVAL;
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}
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dev_priv->sarea_priv = (drm_i915_sarea_t *)
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((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
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if (init->ring_size != 0) {
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if (dev_priv->ring.ring_obj != NULL) {
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i915_dma_cleanup(dev);
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DRM_ERROR("Client tried to initialize ringbuffer in "
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"GEM mode\n");
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return -EINVAL;
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}
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dev_priv->ring.Size = init->ring_size;
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dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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dev_priv->ring.map.offset = init->ring_start;
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dev_priv->ring.map.size = init->ring_size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap_wc(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.virtual == NULL) {
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i915_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return -ENOMEM;
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}
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}
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dev_priv->ring.virtual_start = dev_priv->ring.map.virtual;
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dev_priv->cpp = init->cpp;
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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dev_priv->current_page = 0;
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dev_priv->sarea_priv->pf_current_page = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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return 0;
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}
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static int i915_dma_resume(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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DRM_DEBUG("\n");
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if (!dev_priv->sarea) {
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DRM_ERROR("can not find sarea!\n");
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return -EINVAL;
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}
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if (dev_priv->ring.map.virtual == NULL) {
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return -ENOMEM;
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}
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/* Program Hardware Status Page */
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if (!dev_priv->hw_status_page) {
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DRM_ERROR("Can not find hardware status page\n");
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return -EINVAL;
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}
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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if (dev_priv->status_gfx_addr != 0)
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I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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else
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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DRM_DEBUG("Enabled hardware status page\n");
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return 0;
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}
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static int i915_dma_init(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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drm_i915_init_t *init = data;
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int retcode = 0;
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switch (init->func) {
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case I915_INIT_DMA:
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retcode = i915_initialize(dev, init);
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break;
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case I915_CLEANUP_DMA:
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retcode = i915_dma_cleanup(dev);
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break;
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case I915_RESUME_DMA:
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retcode = i915_dma_resume(dev);
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break;
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default:
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retcode = -EINVAL;
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break;
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}
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return retcode;
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}
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/* Implement basically the same security restrictions as hardware does
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* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
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*
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* Most of the calculations below involve calculating the size of a
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* particular instruction. It's important to get the size right as
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* that tells us where the next instruction to check is. Any illegal
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* instruction detected will be given a size of zero, which is a
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* signal to abort the rest of the buffer.
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*/
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static int do_validate_cmd(int cmd)
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{
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switch (((cmd >> 29) & 0x7)) {
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case 0x0:
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switch ((cmd >> 23) & 0x3f) {
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case 0x0:
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return 1; /* MI_NOOP */
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case 0x4:
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return 1; /* MI_FLUSH */
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default:
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return 0; /* disallow everything else */
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}
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break;
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case 0x1:
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return 0; /* reserved */
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case 0x2:
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return (cmd & 0xff) + 2; /* 2d commands */
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case 0x3:
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if (((cmd >> 24) & 0x1f) <= 0x18)
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return 1;
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switch ((cmd >> 24) & 0x1f) {
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case 0x1c:
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return 1;
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case 0x1d:
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switch ((cmd >> 16) & 0xff) {
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case 0x3:
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return (cmd & 0x1f) + 2;
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case 0x4:
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return (cmd & 0xf) + 2;
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default:
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return (cmd & 0xffff) + 2;
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}
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case 0x1e:
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if (cmd & (1 << 23))
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return (cmd & 0xffff) + 1;
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else
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return 1;
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case 0x1f:
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if ((cmd & (1 << 23)) == 0) /* inline vertices */
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return (cmd & 0x1ffff) + 2;
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else if (cmd & (1 << 17)) /* indirect random */
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if ((cmd & 0xffff) == 0)
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return 0; /* unknown length, too hard */
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else
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return (((cmd & 0xffff) + 1) / 2) + 1;
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else
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return 2; /* indirect sequential */
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default:
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return 0;
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}
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default:
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return 0;
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}
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return 0;
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}
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static int validate_cmd(int cmd)
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{
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int ret = do_validate_cmd(cmd);
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/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
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return ret;
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}
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static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
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int dwords)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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RING_LOCALS;
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if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
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return -EINVAL;
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BEGIN_LP_RING((dwords+1)&~1);
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for (i = 0; i < dwords;) {
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int cmd, sz;
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if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
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return -EINVAL;
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if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
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return -EINVAL;
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OUT_RING(cmd);
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while (++i, --sz) {
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if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
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sizeof(cmd))) {
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return -EINVAL;
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}
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OUT_RING(cmd);
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}
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}
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if (dwords & 1)
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OUT_RING(0);
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ADVANCE_LP_RING();
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return 0;
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}
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int i915_emit_box(struct drm_device * dev,
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struct drm_clip_rect __user * boxes,
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int i, int DR1, int DR4)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_clip_rect box;
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RING_LOCALS;
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if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
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return -EFAULT;
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}
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if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
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DRM_ERROR("Bad box %d,%d..%d,%d\n",
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box.x1, box.y1, box.x2, box.y2);
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return -EINVAL;
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}
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if (IS_I965G(dev)) {
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BEGIN_LP_RING(4);
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OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
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OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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OUT_RING(DR4);
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ADVANCE_LP_RING();
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} else {
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BEGIN_LP_RING(6);
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OUT_RING(GFX_OP_DRAWRECT_INFO);
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OUT_RING(DR1);
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OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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OUT_RING(DR4);
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OUT_RING(0);
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ADVANCE_LP_RING();
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}
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return 0;
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}
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/* XXX: Emitting the counter should really be moved to part of the IRQ
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* emit. For now, do it in both places:
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*/
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static void i915_emit_breadcrumb(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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if (++dev_priv->counter > 0x7FFFFFFFUL)
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dev_priv->counter = 0;
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
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BEGIN_LP_RING(4);
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OUT_RING(MI_STORE_DWORD_INDEX);
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OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(dev_priv->counter);
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OUT_RING(0);
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ADVANCE_LP_RING();
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}
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static int i915_dispatch_cmdbuffer(struct drm_device * dev,
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drm_i915_cmdbuffer_t * cmd)
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{
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int nbox = cmd->num_cliprects;
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int i = 0, count, ret;
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if (cmd->sz & 0x3) {
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DRM_ERROR("alignment\n");
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return -EINVAL;
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}
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i915_kernel_lost_context(dev);
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count = nbox ? nbox : 1;
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for (i = 0; i < count; i++) {
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if (i < nbox) {
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ret = i915_emit_box(dev, cmd->cliprects, i,
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cmd->DR1, cmd->DR4);
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if (ret)
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return ret;
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}
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ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
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if (ret)
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return ret;
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}
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i915_emit_breadcrumb(dev);
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return 0;
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}
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static int i915_dispatch_batchbuffer(struct drm_device * dev,
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drm_i915_batchbuffer_t * batch)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_clip_rect __user *boxes = batch->cliprects;
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int nbox = batch->num_cliprects;
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int i = 0, count;
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RING_LOCALS;
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if ((batch->start | batch->used) & 0x7) {
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DRM_ERROR("alignment\n");
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return -EINVAL;
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}
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i915_kernel_lost_context(dev);
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count = nbox ? nbox : 1;
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|
|
for (i = 0; i < count; i++) {
|
|
if (i < nbox) {
|
|
int ret = i915_emit_box(dev, boxes, i,
|
|
batch->DR1, batch->DR4);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (!IS_I830(dev) && !IS_845G(dev)) {
|
|
BEGIN_LP_RING(2);
|
|
if (IS_I965G(dev)) {
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
|
|
OUT_RING(batch->start);
|
|
} else {
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
}
|
|
ADVANCE_LP_RING();
|
|
} else {
|
|
BEGIN_LP_RING(4);
|
|
OUT_RING(MI_BATCH_BUFFER);
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
OUT_RING(batch->start + batch->used - 4);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
}
|
|
}
|
|
|
|
i915_emit_breadcrumb(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_dispatch_flip(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
RING_LOCALS;
|
|
|
|
if (!dev_priv->sarea_priv)
|
|
return -EINVAL;
|
|
|
|
DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
|
|
__func__,
|
|
dev_priv->current_page,
|
|
dev_priv->sarea_priv->pf_current_page);
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
BEGIN_LP_RING(2);
|
|
OUT_RING(MI_FLUSH | MI_READ_FLUSH);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
BEGIN_LP_RING(6);
|
|
OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
|
|
OUT_RING(0);
|
|
if (dev_priv->current_page == 0) {
|
|
OUT_RING(dev_priv->back_offset);
|
|
dev_priv->current_page = 1;
|
|
} else {
|
|
OUT_RING(dev_priv->front_offset);
|
|
dev_priv->current_page = 0;
|
|
}
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
BEGIN_LP_RING(2);
|
|
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
if (++dev_priv->counter > 0x7FFFFFFFUL)
|
|
dev_priv->counter = 0;
|
|
if (dev_priv->sarea_priv)
|
|
dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
|
|
|
|
BEGIN_LP_RING(4);
|
|
OUT_RING(MI_STORE_DWORD_INDEX);
|
|
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
OUT_RING(dev_priv->counter);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
|
|
return 0;
|
|
}
|
|
|
|
static int i915_quiescent(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
i915_kernel_lost_context(dev);
|
|
return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
|
|
}
|
|
|
|
static int i915_flush_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
int ret;
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
ret = i915_quiescent(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_batchbuffer(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
dev_priv->sarea_priv;
|
|
drm_i915_batchbuffer_t *batch = data;
|
|
size_t cliplen;
|
|
int ret;
|
|
|
|
if (!dev_priv->allow_batchbuffer) {
|
|
DRM_ERROR("Batchbuffer ioctl disabled\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
|
|
batch->start, batch->used, batch->num_cliprects);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
DRM_UNLOCK();
|
|
cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
|
|
if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
|
|
cliplen)) {
|
|
DRM_LOCK();
|
|
return -EFAULT;
|
|
}
|
|
if (batch->num_cliprects) {
|
|
ret = vslock(batch->cliprects, cliplen);
|
|
if (ret) {
|
|
DRM_ERROR("Fault wiring cliprects\n");
|
|
DRM_LOCK();
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
|
|
ret = i915_dispatch_batchbuffer(dev, batch);
|
|
|
|
if (batch->num_cliprects)
|
|
vsunlock(batch->cliprects, cliplen);
|
|
|
|
DRM_LOCK();
|
|
|
|
if (sarea_priv)
|
|
sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_cmdbuffer(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
dev_priv->sarea_priv;
|
|
drm_i915_cmdbuffer_t *cmdbuf = data;
|
|
size_t cliplen;
|
|
int ret;
|
|
|
|
DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
|
|
cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
DRM_UNLOCK();
|
|
cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect);
|
|
if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects,
|
|
cliplen)) {
|
|
DRM_ERROR("Fault accessing cliprects\n");
|
|
DRM_LOCK();
|
|
return -EFAULT;
|
|
}
|
|
if (cmdbuf->num_cliprects) {
|
|
ret = vslock(cmdbuf->cliprects, cliplen);
|
|
if (ret) {
|
|
DRM_ERROR("Fault wiring cliprects\n");
|
|
DRM_LOCK();
|
|
return -EFAULT;
|
|
}
|
|
ret = vslock(cmdbuf->buf, cmdbuf->sz);
|
|
if (ret) {
|
|
vsunlock(cmdbuf->cliprects, cliplen);
|
|
DRM_ERROR("Fault wiring cmds\n");
|
|
DRM_LOCK();
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
|
|
ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
|
|
|
|
if (cmdbuf->num_cliprects) {
|
|
vsunlock(cmdbuf->buf, cmdbuf->sz);
|
|
vsunlock(cmdbuf->cliprects, cliplen);
|
|
}
|
|
DRM_LOCK();
|
|
if (ret) {
|
|
DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
|
|
return ret;
|
|
}
|
|
|
|
if (sarea_priv)
|
|
sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
return 0;
|
|
}
|
|
|
|
static int i915_flip_bufs(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
int ret;
|
|
|
|
DRM_DEBUG("%s\n", __func__);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
ret = i915_dispatch_flip(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_getparam(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_getparam_t *param = data;
|
|
int value;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (param->param) {
|
|
case I915_PARAM_IRQ_ACTIVE:
|
|
value = dev->irq_enabled ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_ALLOW_BATCHBUFFER:
|
|
value = dev_priv->allow_batchbuffer ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_LAST_DISPATCH:
|
|
value = READ_BREADCRUMB(dev_priv);
|
|
break;
|
|
case I915_PARAM_CHIPSET_ID:
|
|
value = dev->pci_device;
|
|
break;
|
|
case I915_PARAM_HAS_GEM:
|
|
/* We need to reset this to 1 once we have GEM */
|
|
value = 0;
|
|
break;
|
|
default:
|
|
DRM_DEBUG("Unknown parameter %d\n", param->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
|
|
DRM_ERROR("DRM_COPY_TO_USER failed\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_setparam(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_setparam_t *param = data;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (param->param) {
|
|
case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
|
|
break;
|
|
case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
|
|
dev_priv->tex_lru_log_granularity = param->value;
|
|
break;
|
|
case I915_SETPARAM_ALLOW_BATCHBUFFER:
|
|
dev_priv->allow_batchbuffer = param->value;
|
|
break;
|
|
default:
|
|
DRM_DEBUG("unknown parameter %d\n", param->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_set_status_page(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_hws_addr_t *hws = data;
|
|
|
|
if (!I915_NEED_GFX_HWS(dev))
|
|
return -EINVAL;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
|
|
|
|
dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
|
|
|
|
dev_priv->hws_map.offset = dev->agp->base + hws->addr;
|
|
dev_priv->hws_map.size = 4*1024;
|
|
dev_priv->hws_map.type = 0;
|
|
dev_priv->hws_map.flags = 0;
|
|
dev_priv->hws_map.mtrr = 0;
|
|
|
|
drm_core_ioremap_wc(&dev_priv->hws_map, dev);
|
|
if (dev_priv->hws_map.virtual == NULL) {
|
|
i915_dma_cleanup(dev);
|
|
dev_priv->status_gfx_addr = 0;
|
|
DRM_ERROR("can not ioremap virtual address for"
|
|
" G33 hw status page\n");
|
|
return -ENOMEM;
|
|
}
|
|
dev_priv->hw_status_page = dev_priv->hws_map.virtual;
|
|
|
|
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
|
|
I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
|
|
DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
|
|
dev_priv->status_gfx_addr);
|
|
DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
|
|
return 0;
|
|
}
|
|
|
|
int i915_driver_load(struct drm_device *dev, unsigned long flags)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
unsigned long base, size;
|
|
int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
|
|
|
|
/* i915 has 4 more counters */
|
|
dev->counters += 4;
|
|
dev->types[6] = _DRM_STAT_IRQ;
|
|
dev->types[7] = _DRM_STAT_PRIMARY;
|
|
dev->types[8] = _DRM_STAT_SECONDARY;
|
|
dev->types[9] = _DRM_STAT_DMA;
|
|
|
|
dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
|
|
if (dev_priv == NULL)
|
|
return -ENOMEM;
|
|
|
|
memset(dev_priv, 0, sizeof(drm_i915_private_t));
|
|
|
|
dev->dev_private = (void *)dev_priv;
|
|
dev_priv->dev = dev;
|
|
|
|
/* Add register map (needed for suspend/resume) */
|
|
base = drm_get_resource_start(dev, mmio_bar);
|
|
size = drm_get_resource_len(dev, mmio_bar);
|
|
|
|
ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
|
|
_DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
|
|
|
|
if (IS_G4X(dev)) {
|
|
dev->driver->get_vblank_counter = g45_get_vblank_counter;
|
|
dev->max_vblank_count = 0xffffffff; /* 32 bits of frame count */
|
|
} else {
|
|
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
|
dev->max_vblank_count = 0x00ffffff; /* 24 bits of frame count */
|
|
}
|
|
|
|
#ifdef I915_HAVE_GEM
|
|
i915_gem_load(dev);
|
|
#endif
|
|
/* Init HWS */
|
|
if (!I915_NEED_GFX_HWS(dev)) {
|
|
ret = i915_init_phys_hws(dev);
|
|
if (ret != 0) {
|
|
drm_rmmap(dev, dev_priv->mmio_map);
|
|
drm_free(dev_priv, sizeof(struct drm_i915_private),
|
|
DRM_MEM_DRIVER);
|
|
return ret;
|
|
}
|
|
}
|
|
#ifdef __linux__
|
|
/* On the 945G/GM, the chipset reports the MSI capability on the
|
|
* integrated graphics even though the support isn't actually there
|
|
* according to the published specs. It doesn't appear to function
|
|
* correctly in testing on 945G.
|
|
* This may be a side effect of MSI having been made available for PEG
|
|
* and the registers being closely associated.
|
|
*
|
|
* According to chipset errata, on the 965GM, MSI interrupts may
|
|
* be lost or delayed
|
|
*/
|
|
if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
|
|
if (pci_enable_msi(dev->pdev))
|
|
DRM_ERROR("failed to enable MSI\n");
|
|
|
|
intel_opregion_init(dev);
|
|
#endif
|
|
DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
|
|
dev_priv->user_irq_refcount = 0;
|
|
|
|
ret = drm_vblank_init(dev, I915_NUM_PIPE);
|
|
|
|
if (ret) {
|
|
(void) i915_driver_unload(dev);
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int i915_driver_unload(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
i915_free_hws(dev);
|
|
|
|
drm_rmmap(dev, dev_priv->mmio_map);
|
|
#ifdef __linux__
|
|
intel_opregion_free(dev);
|
|
#endif
|
|
DRM_SPINUNINIT(&dev_priv->user_irq_lock);
|
|
|
|
drm_free(dev->dev_private, sizeof(drm_i915_private_t),
|
|
DRM_MEM_DRIVER);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
|
|
{
|
|
struct drm_i915_file_private *i915_file_priv;
|
|
|
|
DRM_DEBUG("\n");
|
|
i915_file_priv = (struct drm_i915_file_private *)
|
|
drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
|
|
|
|
if (!i915_file_priv)
|
|
return -ENOMEM;
|
|
|
|
file_priv->driver_priv = i915_file_priv;
|
|
|
|
i915_file_priv->mm.last_gem_seqno = 0;
|
|
i915_file_priv->mm.last_gem_throttle_seqno = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void i915_driver_lastclose(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev_priv)
|
|
return;
|
|
#ifdef I915_HAVE_GEM
|
|
i915_gem_lastclose(dev);
|
|
#endif
|
|
if (dev_priv->agp_heap)
|
|
i915_mem_takedown(&(dev_priv->agp_heap));
|
|
|
|
i915_dma_cleanup(dev);
|
|
}
|
|
|
|
void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
i915_mem_release(dev, file_priv, dev_priv->agp_heap);
|
|
}
|
|
|
|
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
|
|
{
|
|
struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
|
|
|
|
drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
|
|
}
|
|
|
|
struct drm_ioctl_desc i915_ioctls[] = {
|
|
DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
|
|
DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
|
|
DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
|
|
DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
#ifdef I915_HAVE_GEM
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
|
|
DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
|
|
#endif
|
|
};
|
|
|
|
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
|
|
|
|
/**
|
|
* Determine if the device really is AGP or not.
|
|
*
|
|
* All Intel graphics chipsets are treated as AGP, even if they are really
|
|
* PCI-e.
|
|
*
|
|
* \param dev The device to be tested.
|
|
*
|
|
* \returns
|
|
* A value of 1 is always retured to indictate every i9x5 is AGP.
|
|
*/
|
|
int i915_driver_device_is_agp(struct drm_device * dev)
|
|
{
|
|
return 1;
|
|
}
|