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90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*-
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* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AMD64_SGX_SGXVAR_H_
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#define _AMD64_SGX_SGXVAR_H_
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#define SGX_CPUID 0x12
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#define SGX_PAGE_SIZE 4096
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#define SGX_VA_PAGE_SLOTS 512
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#define SGX_VA_PAGES_OFFS 512
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#define SGX_SECS_VM_OBJECT_INDEX -1
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#define SGX_SIGSTRUCT_SIZE 1808
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#define SGX_EINITTOKEN_SIZE 304
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#define SGX_IOCTL_MAX_DATA_LEN 26
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#define SGX_ENCL_SIZE_MAX_DEF 0x1000000000ULL
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#define SGX_EFAULT 99
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#ifndef LOCORE
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static MALLOC_DEFINE(M_SGX, "sgx", "SGX driver");
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struct sgx_vm_handle {
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struct sgx_softc *sc;
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vm_object_t mem;
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uint64_t base;
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vm_size_t size;
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struct sgx_enclave *enclave;
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};
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/* EPC (Enclave Page Cache) page. */
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struct epc_page {
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uint64_t base;
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uint64_t phys;
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int index;
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};
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struct sgx_enclave {
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uint64_t base;
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uint64_t size;
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struct sgx_vm_handle *vmh;
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TAILQ_ENTRY(sgx_enclave) next;
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vm_object_t object;
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struct epc_page *secs_epc_page;
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};
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struct sgx_softc {
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struct cdev *sgx_cdev;
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struct mtx mtx_encls;
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struct mtx mtx;
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uint64_t epc_base;
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uint64_t epc_size;
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struct epc_page *epc_pages;
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struct vmem *vmem_epc;
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uint32_t npages;
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TAILQ_HEAD(, sgx_enclave) enclaves;
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uint64_t enclave_size_max;
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uint8_t state;
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#define SGX_STATE_RUNNING (1 << 0)
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};
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#endif /* !LOCORE */
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#endif /* !_AMD64_SGX_SGXVAR_H_ */
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