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228 lines
10 KiB
C
228 lines
10 KiB
C
/* $Id$ */
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/* $NetBSD: ioasicreg.h,v 1.2 1997/04/06 22:30:28 cgd Exp $ */
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/*
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* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* The Mach Operating System project at Carnegie-Mellon University,
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)asic.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Slot definitions
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*/
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#define IOASIC_SLOT_0_START 0x000000
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#define IOASIC_SLOT_1_START 0x040000
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#define IOASIC_SLOT_2_START 0x080000
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#define IOASIC_SLOT_3_START 0x0c0000
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#define IOASIC_SLOT_4_START 0x100000
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#define IOASIC_SLOT_5_START 0x140000
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#define IOASIC_SLOT_6_START 0x180000
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#define IOASIC_SLOT_7_START 0x1c0000
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#define IOASIC_SLOT_8_START 0x200000
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#define IOASIC_SLOT_9_START 0x240000
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#define IOASIC_SLOT_10_START 0x280000
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#define IOASIC_SLOT_11_START 0x2c0000
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#define IOASIC_SLOT_12_START 0x300000
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#define IOASIC_SLOT_13_START 0x340000
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#define IOASIC_SLOT_14_START 0x380000
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#define IOASIC_SLOT_15_START 0x3c0000
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#define IOASIC_SLOTS_END 0x3fffff
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/*
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* Register offsets (slot 1)
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*/
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#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
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#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
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#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
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#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
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#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
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#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
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#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
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#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
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#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
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#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
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#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
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#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
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#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
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#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
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#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
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#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
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#define IOASIC_CSR IOASIC_SLOT_1_START+0x100
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#define IOASIC_INTR IOASIC_SLOT_1_START+0x110
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#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
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#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
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#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
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#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
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#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
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#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
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#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
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#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
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#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
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#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
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#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
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#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
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/* System Status and control Register (SSR). */
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#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
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#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
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#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
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#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
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#define IOASIC_CSR_FASTMODE 0x08000000 /* rw */
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#define IOASIC_CSR_xxx 0x07800000 /* unused/reserved */
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#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw */
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#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw */
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#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
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#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
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#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw */
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#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw */
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#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw */
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/* low 16 bits are rw gp outputs */
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/* System Interrupt Register (and Interrupt Mask Register). */
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#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
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#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
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#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
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#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
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#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
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#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
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#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
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#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
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#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz */
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#define IOASIC_INTR_ISDN_PTR_LOAD 0x00400000 /* rz */
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#define IOASIC_INTR_ISDN_OVRUN 0x00200000 /* rz */
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#define IOASIC_INTR_ISDN_READ_E 0x00100000 /* rz */
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#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz */
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#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz */
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#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz */
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#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz */
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#define IOASIC_INTR_ISDN 0x00002000 /* ro */
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#define IOASIC_INTR_SEC_CON 0x00000200 /* ro */
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#define IOASIC_INTR_LANCE 0x00000100 /* ro */
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#define IOASIC_INTR_SCC_1 0x00000080 /* ro */
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#define IOASIC_INTR_SCC_0 0x00000040 /* ro */
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#define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */
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#define IOASIC_INTR_300_OPT1 IOASIC_INTR_ALT_CON /* ro - 3000/300 */
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#define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */
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/* DMA pointer registers (SCSI, Comm, ...) */
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#define IOASIC_DMAPTR_MASK 0xffffffe0
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#define IOASIC_DMAPTR_SHIFT 5
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#define IOASIC_DMAPTR_SET(reg,val) \
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(reg) = (((val)<<IOASIC_DMAPTR_SHIFT)&IOASIC_DMAPTR_MASK)
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#define IOASIC_DMAPTR_GET(reg,val) \
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(val) = (((reg)&IOASIC_DMAPTR_MASK)>>IOASIC_DMAPTR_SHIFT)
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#define IOASIC_DMA_ADDR(p) (((unsigned)p) << (5-2))
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/* For the LANCE DMA pointer register initialization the above suffices */
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/* More SCSI DMA registers */
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#define IOASIC_SCR_STATUS 0x00000004
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#define IOASIC_SCR_WORD 0x00000003
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/* Various Decode registers */
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#define IOASIC_DECODE_HW_ADDRESS 0x000003f0
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#define IOASIC_DECODE_CHIP_SELECT 0x0000000f
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/*
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* Asic register addresses at offset from base.
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*/
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#define IOASIC_REG_SCSI_DMAPTR(base) ((base) + IOASIC_SCSI_DMAPTR)
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#define IOASIC_REG_SCSI_DMANPTR(base) ((base) + IOASIC_SCSI_NEXTPTR)
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#define IOASIC_REG_LANCE_DMAPTR(base) ((base) + IOASIC_LANCE_DMAPTR)
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#define IOASIC_REG_SCC_T1_DMAPTR(base) ((base) + IOASIC_SCC_T1_DMAPTR)
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#define IOASIC_REG_SCC_R1_DMAPTR(base) ((base) + IOASIC_SCC_R1_DMAPTR)
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#define IOASIC_REG_SCC_T2_DMAPTR(base) ((base) + IOASIC_SCC_T2_DMAPTR)
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#define IOASIC_REG_SCC_R2_DMAPTR(base) ((base) + IOASIC_SCC_R2_DMAPTR)
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#define IOASIC_REG_FLOPPY_DMAPTR(base) ((base) + IOASIC_FLOPPY_DMAPTR)
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#define IOASIC_REG_ISDN_X_DMAPTR(base) ((base) + IOASIC_ISDN_X_DMAPTR)
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#define IOASIC_REG_ISDN_X_NEXTPTR(base) ((base) + IOASIC_ISDN_X_NEXTPTR)
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#define IOASIC_REG_ISDN_R_DMAPTR(base) ((base) + IOASIC_ISDN_R_DMAPTR)
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#define IOASIC_REG_ISDN_R_NEXTPTR(base) ((base) + IOASIC_ISDN_R_NEXTPTR)
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#define IOASIC_REG_BUFF0(base) ((base) + IOASIC_BUFF0)
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#define IOASIC_REG_BUFF1(base) ((base) + IOASIC_BUFF1)
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#define IOASIC_REG_BUFF2(base) ((base) + IOASIC_BUFF2)
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#define IOASIC_REG_BUFF3(base) ((base) + IOASIC_BUFF3)
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#define IOASIC_REG_CSR(base) ((base) + IOASIC_CSR)
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#define IOASIC_REG_INTR(base) ((base) + IOASIC_INTR)
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#define IOASIC_REG_IMSK(base) ((base) + IOASIC_IMSK)
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#define IOASIC_REG_CURADDR(base) ((base) + IOASIC_CURADDR)
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#define IOASIC_REG_ISDN_X_DATA(base) ((base) + IOASIC_ISDN_X_DATA)
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#define IOASIC_REG_ISDN_R_DATA(base) ((base) + IOASIC_ISDN_R_DATA)
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#define IOASIC_REG_LANCE_DECODE(base) ((base) + IOASIC_LANCE_DECODE)
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#define IOASIC_REG_SCSI_DECODE(base) ((base) + IOASIC_SCSI_DECODE)
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#define IOASIC_REG_SCC0_DECODE(base) ((base) + IOASIC_SCC0_DECODE)
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#define IOASIC_REG_SCC1_DECODE(base) ((base) + IOASIC_SCC1_DECODE)
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#define IOASIC_REG_FLOPPY_DECODE(base) ((base) + IOASIC_FLOPPY_DECODE)
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#define IOASIC_REG_SCSI_SCR(base) ((base) + IOASIC_SCSI_SCR)
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#define IOASIC_REG_SCSI_SDR0(base) ((base) + IOASIC_SCSI_SDR0)
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#define IOASIC_REG_SCSI_SDR1(base) ((base) + IOASIC_SCSI_SDR1)
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/*
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* And slot assignments.
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*/
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#define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
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#define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)
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