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590 lines
13 KiB
C
590 lines
13 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* Copyright (c) 2004, Scott Long <scottl@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/pc/bios.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_extern.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h>
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#define PRVERB(a) do { \
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if (bootverbose) \
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printf a ; \
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} while(0)
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#define PCIE_CACHE 8
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struct pcie_cfg_elem {
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TAILQ_ENTRY(pcie_cfg_elem) elem;
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vm_offset_t vapage;
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vm_paddr_t papage;
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};
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enum {
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CFGMECH_NONE = 0,
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CFGMECH_1,
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CFGMECH_2,
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CFGMECH_PCIE,
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};
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static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
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static uint32_t pciebar;
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static int cfgmech;
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static int devmax;
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static struct mtx pcicfg_mtx;
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static int pciereg_cfgopen(void);
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static int pciereg_cfgread(int bus, int slot, int func, int reg,
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int bytes);
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static void pciereg_cfgwrite(int bus, int slot, int func, int reg,
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int data, int bytes);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Some use
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* numbers in the range 128-254 to indicate something strange and
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* apparently undocumented anywhere. Assume these are completely bogus
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* and map them to 255, which means "none".
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*/
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static __inline int
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pci_i386_map_intline(int line)
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{
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if (line == 0 || line >= 128)
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return (PCI_INVALID_IRQ);
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return (line);
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}
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static u_int16_t
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pcibios_get_version(void)
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{
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struct bios_regs args;
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if (PCIbios.ventry == 0) {
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PRVERB(("pcibios: No call entry point\n"));
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return (0);
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}
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args.eax = PCIBIOS_BIOS_PRESENT;
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if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
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PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
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return (0);
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}
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if (args.edx != 0x20494350) {
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PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
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return (0);
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}
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return (args.ebx & 0xffff);
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}
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/*
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* Initialise access to PCI configuration space
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*/
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int
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pci_cfgregopen(void)
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{
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static int opened = 0;
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u_int16_t vid, did;
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u_int16_t v;
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if (opened)
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return(1);
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if (pcireg_cfgopen() == 0)
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return(0);
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v = pcibios_get_version();
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if (v > 0)
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PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
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v & 0xff));
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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opened = 1;
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/* $PIR requires PCI BIOS 2.10 or greater. */
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if (v >= 0x0210)
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pci_pir_open();
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/*
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* Grope around in the PCI config space to see if this is a
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* chipset that is capable of doing memory-mapped config cycles.
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* This also implies that it can do PCIe extended config cycles.
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*/
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/* Check for the Intel 7520 and 925 chipsets */
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vid = pci_cfgregread(0, 0, 0, 0x0, 2);
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did = pci_cfgregread(0, 0, 0, 0x2, 2);
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if ((vid == 0x8086) && (did == 0x3590)) {
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pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
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pciereg_cfgopen();
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} else if ((vid == 0x8086) && (did == 0x2580)) {
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pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
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pciereg_cfgopen();
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}
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return(1);
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}
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/*
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* Read configuration space register
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*/
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line;
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. The rest of
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* the code uses 255 as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
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return (pci_i386_map_intline(line));
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}
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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* Configuration space access using direct register operations
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*/
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes - 1)) == 0) {
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switch (cfgmech) {
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case CFGMECH_1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case CFGMECH_2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case CFGMECH_1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case CFGMECH_2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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}
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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data = pciereg_cfgread(bus, slot, func, reg, bytes);
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return (data);
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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if (cfgmech == CFGMECH_PCIE) {
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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/* check whether the configuration mechanism has been correctly identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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uint32_t id, class;
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uint8_t header;
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uint8_t device;
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int port;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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if (bootverbose)
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printf("%d ", device);
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port = pci_cfgenable(0, device, 0, 0, 4);
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id = inl(port);
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if (id == 0 || id == 0xffffffff)
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continue;
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port = pci_cfgenable(0, device, 0, 8, 4);
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class = inl(port) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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port = pci_cfgenable(0, device, 0, 14, 1);
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header = inb(port);
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pcireg_cfgopen(void)
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{
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uint32_t mode1res, oldval1;
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uint8_t mode2res, oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = CFGMECH_1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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DELAY(1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = CFGMECH_2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = CFGMECH_NONE;
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devmax = 0;
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return (cfgmech);
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}
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static int
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pciereg_cfgopen(void)
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{
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struct pcie_cfg_list *pcielist;
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struct pcie_cfg_elem *pcie_array, *elem;
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#ifdef SMP
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struct pcpu *pc;
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#endif
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vm_offset_t va;
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int i;
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if (bootverbose)
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printf("Setting up PCIe mappings for BAR 0x%x\n", pciebar);
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#ifdef SMP
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SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
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#endif
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{
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pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
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M_DEVBUF, M_NOWAIT);
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if (pcie_array == NULL)
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return (0);
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va = kmem_alloc_nofault(kernel_map, PCIE_CACHE * PAGE_SIZE);
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if (va == 0) {
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free(pcie_array, M_DEVBUF);
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return (0);
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}
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#ifdef SMP
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pcielist = &pcie_list[pc->pc_cpuid];
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#else
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pcielist = &pcie_list[0];
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#endif
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TAILQ_INIT(pcielist);
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for (i = 0; i < PCIE_CACHE; i++) {
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elem = &pcie_array[i];
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elem->vapage = va + (i * PAGE_SIZE);
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elem->papage = 0;
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TAILQ_INSERT_HEAD(pcielist, elem, elem);
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}
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}
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cfgmech = CFGMECH_PCIE;
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devmax = 32;
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return (1);
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}
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#define PCIE_PADDR(bar, reg, bus, slot, func) \
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((bar) | \
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(((bus) & 0xff) << 20) | \
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(((slot) & 0x1f) << 15) | \
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(((func) & 0x7) << 12) | \
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((reg) & 0xfff))
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/*
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* Find an element in the cache that matches the physical page desired, or
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* create a new mapping from the least recently used element.
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* A very simple LRU algorithm is used here, does it need to be more
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* efficient?
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*/
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static __inline struct pcie_cfg_elem *
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pciereg_findelem(vm_paddr_t papage)
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{
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struct pcie_cfg_list *pcielist;
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struct pcie_cfg_elem *elem;
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pcielist = &pcie_list[PCPU_GET(cpuid)];
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TAILQ_FOREACH(elem, pcielist, elem) {
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if (elem->papage == papage)
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break;
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}
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if (elem == NULL) {
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elem = TAILQ_LAST(pcielist, pcie_cfg_list);
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if (elem->papage != 0) {
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pmap_kremove(elem->vapage);
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invlpg(elem->vapage);
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}
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pmap_kenter(elem->vapage, papage);
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elem->papage = papage;
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}
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if (elem != TAILQ_FIRST(pcielist)) {
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TAILQ_REMOVE(pcielist, elem, elem);
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TAILQ_INSERT_HEAD(pcielist, elem, elem);
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}
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return (elem);
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}
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static int
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pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
|
|
{
|
|
struct pcie_cfg_elem *elem;
|
|
volatile vm_offset_t va;
|
|
vm_paddr_t pa, papage;
|
|
int data;
|
|
|
|
critical_enter();
|
|
pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
|
|
papage = pa & ~PAGE_MASK;
|
|
elem = pciereg_findelem(papage);
|
|
va = elem->vapage | (pa & PAGE_MASK);
|
|
|
|
switch (bytes) {
|
|
case 4:
|
|
data = *(volatile uint32_t *)(va);
|
|
break;
|
|
case 2:
|
|
data = *(volatile uint16_t *)(va);
|
|
break;
|
|
case 1:
|
|
data = *(volatile uint8_t *)(va);
|
|
break;
|
|
default:
|
|
panic("pciereg_cfgread: invalid width");
|
|
}
|
|
|
|
critical_exit();
|
|
return (data);
|
|
}
|
|
|
|
static void
|
|
pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
|
|
{
|
|
struct pcie_cfg_elem *elem;
|
|
volatile vm_offset_t va;
|
|
vm_paddr_t pa, papage;
|
|
|
|
critical_enter();
|
|
pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
|
|
papage = pa & ~PAGE_MASK;
|
|
elem = pciereg_findelem(papage);
|
|
va = elem->vapage | (pa & PAGE_MASK);
|
|
|
|
switch (bytes) {
|
|
case 4:
|
|
*(volatile uint32_t *)(va) = data;
|
|
break;
|
|
case 2:
|
|
*(volatile uint16_t *)(va) = data;
|
|
break;
|
|
case 1:
|
|
*(volatile uint8_t *)(va) = data;
|
|
break;
|
|
default:
|
|
panic("pciereg_cfgwrite: invalid width");
|
|
}
|
|
|
|
critical_exit();
|
|
}
|