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231 lines
7.4 KiB
C
231 lines
7.4 KiB
C
/*-
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* Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Berkeley Software Design Inc's name may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ASI_H_
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#define _MACHINE_ASI_H_
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/*
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* Standard v9 asis
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*/
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#define ASI_N 0x4
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#define ASI_NL 0xc
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#define ASI_AIUP 0x10
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#define ASI_AIUS 0x11
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#define ASI_AIUPL 0x18
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#define ASI_AIUSL 0x19
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#define ASI_P 0x80
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#define ASI_S 0x81
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#define ASI_PNF 0x82
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#define ASI_SNF 0x83
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#define ASI_PL 0x88
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#define ASI_SL 0x89
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#define ASI_PNFL 0x8a
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#define ASI_SNFL 0x8b
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/*
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* UltraSPARC extensions. ASIs limited to a certain family are annotated.
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*/
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#define ASI_PHYS_USE_EC 0x14
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#define ASI_PHYS_BYPASS_EC_WITH_EBIT 0x15
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#define ASI_PHYS_USE_EC_L 0x1c
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#define ASI_PHYS_BYPASS_EC_WITH_EBIT_L 0x1d
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#define ASI_NUCLEUS_QUAD_LDD 0x24
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#define ASI_NUCLEUS_QUAD_LDD_L 0x2c
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#define ASI_PCACHE_STATUS_DATA 0x30 /* US-III Cu */
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#define ASI_PCACHE_DATA 0x31 /* US-III Cu */
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#define ASI_PCACHE_TAG 0x32 /* US-III Cu */
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#define ASI_PCACHE_SNOOP_TAG 0x33 /* US-III Cu */
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#define ASI_ATOMIC_QUAD_LDD_PHYS 0x34 /* US-III Cu */
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#define ASI_WCACHE_VALID_BITS 0x38 /* US-III Cu */
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#define ASI_WCACHE_DATA 0x39 /* US-III Cu */
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#define ASI_WCACHE_TAG 0x3a /* US-III Cu */
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#define ASI_WCACHE_SNOOP_TAG 0x3b /* US-III Cu */
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#define ASI_ATOMIC_QUAD_LDD_PHYS_L 0x3c /* US-III Cu */
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#define ASI_SRAM_FAST_INIT 0x40 /* US-III Cu */
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#define ASI_DCACHE_INVALIDATE 0x42 /* US-III Cu */
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#define ASI_DCACHE_UTAG 0x43 /* US-III Cu */
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#define ASI_DCACHE_SNOOP_TAG 0x44 /* US-III Cu */
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/* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
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#define ASI_LSU_CTL_REG 0x45
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#define ASI_DCACHE_DATA 0x46
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#define ASI_DCACHE_TAG 0x47
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#define ASI_INTR_DISPATCH_STATUS 0x48
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#define ASI_INTR_RECEIVE 0x49
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#define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */
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#define ASI_FIREPLANE_CONFIG_REG 0x4a /* US-III Cu */
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#define AA_FIREPLANE_CONFIG 0x0 /* US-III Cu */
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#define AA_FIREPLANE_ADDRESS 0x8 /* US-III Cu */
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#define ASI_ESTATE_ERROR_EN_REG 0x4b
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#define ASI_AFSR 0x4c
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#define ASI_AFAR 0x4d
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#define ASI_ECACHE_TAG_DATA 0x4e
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#define ASI_IMMU_TAG_TARGET_REG 0x50
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#define ASI_IMMU 0x50
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#define AA_IMMU_TTR 0x0
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#define AA_IMMU_SFSR 0x18
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#define AA_IMMU_TSB 0x28
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#define AA_IMMU_TAR 0x30
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#define AA_IMMU_TSB_PEXT_REG 0x48 /* US-III family */
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#define AA_IMMU_TSB_SEXT_REG 0x50 /* US-III family */
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#define AA_IMMU_TSB_NEXT_REG 0x58 /* US-III family */
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#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
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#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
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#define ASI_SERIAL_ID 0x53 /* US-III family */
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#define ASI_ITLB_DATA_IN_REG 0x54
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/* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
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#define ASI_ITLB_DATA_ACCESS_REG 0x55
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#define ASI_ITLB_TAG_READ_REG 0x56
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#define ASI_IMMU_DEMAP 0x57
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#define ASI_DMMU_TAG_TARGET_REG 0x58
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#define ASI_DMMU 0x58
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#define AA_DMMU_TTR 0x0
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#define AA_DMMU_PCXR 0x8
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#define AA_DMMU_SCXR 0x10
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#define AA_DMMU_SFSR 0x18
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#define AA_DMMU_SFAR 0x20
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#define AA_DMMU_TSB 0x28
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#define AA_DMMU_TAR 0x30
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#define AA_DMMU_VWPR 0x38
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#define AA_DMMU_PWPR 0x40
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#define AA_DMMU_TSB_PEXT_REG 0x48
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#define AA_DMMU_TSB_SEXT_REG 0x50
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#define AA_DMMU_TSB_NEXT_REG 0x58
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#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
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#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
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#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
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#define ASI_DTLB_DATA_IN_REG 0x5c
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/* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
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#define ASI_DTLB_DATA_ACCESS_REG 0x5d
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#define ASI_DTLB_TAG_READ_REG 0x5e
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#define ASI_DMMU_DEMAP 0x5f
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#define ASI_IIU_INST_TRAP 0x60 /* US-III family */
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#define ASI_ICACHE_INSTR 0x66
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#define ASI_ICACHE_TAG 0x67
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#define ASI_ICACHE_SNOOP_TAG 0x68 /* US-III family */
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#define ASI_ICACHE_PRE_DECODE 0x6e /* US-I, II */
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#define ASI_ICACHE_PRE_NEXT_FIELD 0x6f /* US-I, II */
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#define ASI_BLK_AUIP 0x70
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#define ASI_BLK_AIUS 0x71
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#define ASI_MCU_CONFIG_REG 0x72 /* US-III Cu */
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#define AA_MCU_TIMING1_REG 0x0 /* US-III Cu */
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#define AA_MCU_TIMING2_REG 0x8 /* US-III Cu */
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#define AA_MCU_TIMING3_REG 0x10 /* US-III Cu */
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#define AA_MCU_TIMING4_REG 0x18 /* US-III Cu */
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#define AA_MCU_DEC1_REG 0x20 /* US-III Cu */
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#define AA_MCU_DEC2_REG 0x28 /* US-III Cu */
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#define AA_MCU_DEC3_REG 0x30 /* US-III Cu */
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#define AA_MCU_DEC4_REG 0x38 /* US-III Cu */
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#define AA_MCU_ADDR_CNTL_REG 0x40 /* US-III Cu */
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#define ASI_ECACHE_DATA 0x74 /* US-III Cu */
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#define ASI_ECACHE_CONTROL 0x75 /* US-III Cu */
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#define ASI_ECACHE_W 0x76
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/*
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* With the advent of the US-III, the numbering has changed, as additional
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* registers were inserted in between. We retain the original ordering for
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* now, and append an A to the inserted registers.
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* Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended
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* at the end.
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*/
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#define ASI_SDB_INTR_W 0x77
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#define AA_SDB_INTR_D0 0x40
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#define AA_SDB_INTR_D0A 0x48 /* US-III family */
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#define AA_SDB_INTR_D1 0x50
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#define AA_SDB_INTR_D1A 0x5A /* US-III family */
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#define AA_SDB_INTR_D2 0x60
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#define AA_SDB_INTR_D2A 0x68 /* US-III family */
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#define AA_INTR_SEND 0x70
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#define AA_SDB_INTR_D6 0x80 /* US-III family */
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#define AA_SDB_INTR_D7 0x88 /* US-III family */
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#define ASI_BLK_AIUPL 0x78
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#define ASI_BLK_AIUSL 0x79
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#define ASI_ECACHE_R 0x7e
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#define ASI_SDB_INTR_R 0x7f
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#define ASI_PST8_P 0xc0
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#define ASI_PST8_S 0xc1
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#define ASI_PST16_P 0xc2
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#define ASI_PST16_S 0xc3
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#define ASI_PST32_P 0xc4
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#define ASI_PST32_S 0xc5
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#define ASI_PST8_PL 0xc8
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#define ASI_PST8_SL 0xc9
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#define ASI_PST16_PL 0xca
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#define ASI_PST16_SL 0xcb
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#define ASI_PST32_PL 0xcc
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#define ASI_PST32_SL 0xcd
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#define ASI_FL8_P 0xd0
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#define ASI_FL8_S 0xd1
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#define ASI_FL16_P 0xd2
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#define ASI_FL16_S 0xd3
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#define ASI_FL8_PL 0xd8
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#define ASI_FL8_SL 0xd9
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#define ASI_FL16_PL 0xda
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#define ASI_FL16_SL 0xdb
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#define ASI_BLK_COMMIT_P 0xe0
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#define ASI_BLK_COMMIT_S 0xe1
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#define ASI_BLK_P 0xf0
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#define ASI_BLK_S 0xf1
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#define ASI_BLK_PL 0xf8
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#define ASI_BLK_SL 0xf9
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#endif /* !_MACHINE_ASI_H_ */
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