368 lines
9.9 KiB
C
368 lines
9.9 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_fman_tgec.h"
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void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *adr)
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{
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uint32_t tmp0, tmp1;
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tmp0 = (uint32_t)(adr[0] |
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adr[1] << 8 |
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adr[2] << 16 |
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adr[3] << 24);
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tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
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iowrite32be(tmp0, ®s->mac_addr_0);
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iowrite32be(tmp1, ®s->mac_addr_1);
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}
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void fman_tgec_reset_stat(struct tgec_regs *regs)
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{
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uint32_t tmp;
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tmp = ioread32be(®s->command_config);
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tmp |= CMD_CFG_STAT_CLR;
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iowrite32be(tmp, ®s->command_config);
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while (ioread32be(®s->command_config) & CMD_CFG_STAT_CLR) ;
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}
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#define GET_TGEC_CNTR_64(bn) \
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(((uint64_t)ioread32be(®s->bn ## _u) << 32) | \
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ioread32be(®s->bn ## _l))
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uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name)
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{
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uint64_t ret_val;
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switch (reg_name) {
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case E_TGEC_COUNTER_R64:
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ret_val = GET_TGEC_CNTR_64(r64);
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break;
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case E_TGEC_COUNTER_R127:
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ret_val = GET_TGEC_CNTR_64(r127);
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break;
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case E_TGEC_COUNTER_R255:
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ret_val = GET_TGEC_CNTR_64(r255);
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break;
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case E_TGEC_COUNTER_R511:
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ret_val = GET_TGEC_CNTR_64(r511);
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break;
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case E_TGEC_COUNTER_R1023:
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ret_val = GET_TGEC_CNTR_64(r1023);
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break;
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case E_TGEC_COUNTER_R1518:
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ret_val = GET_TGEC_CNTR_64(r1518);
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break;
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case E_TGEC_COUNTER_R1519X:
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ret_val = GET_TGEC_CNTR_64(r1519x);
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break;
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case E_TGEC_COUNTER_TRFRG:
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ret_val = GET_TGEC_CNTR_64(trfrg);
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break;
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case E_TGEC_COUNTER_TRJBR:
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ret_val = GET_TGEC_CNTR_64(trjbr);
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break;
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case E_TGEC_COUNTER_RDRP:
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ret_val = GET_TGEC_CNTR_64(rdrp);
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break;
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case E_TGEC_COUNTER_RALN:
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ret_val = GET_TGEC_CNTR_64(raln);
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break;
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case E_TGEC_COUNTER_TRUND:
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ret_val = GET_TGEC_CNTR_64(trund);
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break;
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case E_TGEC_COUNTER_TROVR:
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ret_val = GET_TGEC_CNTR_64(trovr);
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break;
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case E_TGEC_COUNTER_RXPF:
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ret_val = GET_TGEC_CNTR_64(rxpf);
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break;
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case E_TGEC_COUNTER_TXPF:
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ret_val = GET_TGEC_CNTR_64(txpf);
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break;
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case E_TGEC_COUNTER_ROCT:
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ret_val = GET_TGEC_CNTR_64(roct);
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break;
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case E_TGEC_COUNTER_RMCA:
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ret_val = GET_TGEC_CNTR_64(rmca);
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break;
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case E_TGEC_COUNTER_RBCA:
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ret_val = GET_TGEC_CNTR_64(rbca);
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break;
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case E_TGEC_COUNTER_RPKT:
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ret_val = GET_TGEC_CNTR_64(rpkt);
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break;
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case E_TGEC_COUNTER_RUCA:
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ret_val = GET_TGEC_CNTR_64(ruca);
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break;
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case E_TGEC_COUNTER_RERR:
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ret_val = GET_TGEC_CNTR_64(rerr);
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break;
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case E_TGEC_COUNTER_TOCT:
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ret_val = GET_TGEC_CNTR_64(toct);
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break;
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case E_TGEC_COUNTER_TMCA:
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ret_val = GET_TGEC_CNTR_64(tmca);
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break;
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case E_TGEC_COUNTER_TBCA:
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ret_val = GET_TGEC_CNTR_64(tbca);
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break;
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case E_TGEC_COUNTER_TUCA:
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ret_val = GET_TGEC_CNTR_64(tuca);
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break;
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case E_TGEC_COUNTER_TERR:
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ret_val = GET_TGEC_CNTR_64(terr);
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break;
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default:
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ret_val = 0;
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}
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return ret_val;
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}
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void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
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{
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uint32_t tmp;
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tmp = ioread32be(®s->command_config);
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if (apply_rx)
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tmp |= CMD_CFG_RX_EN;
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if (apply_tx)
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tmp |= CMD_CFG_TX_EN;
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iowrite32be(tmp, ®s->command_config);
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}
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void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
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{
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uint32_t tmp_reg_32;
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tmp_reg_32 = ioread32be(®s->command_config);
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if (apply_rx)
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tmp_reg_32 &= ~CMD_CFG_RX_EN;
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if (apply_tx)
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tmp_reg_32 &= ~CMD_CFG_TX_EN;
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iowrite32be(tmp_reg_32, ®s->command_config);
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}
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void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val)
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{
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uint32_t tmp;
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tmp = ioread32be(®s->command_config);
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if (val)
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tmp |= CMD_CFG_PROMIS_EN;
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else
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tmp &= ~CMD_CFG_PROMIS_EN;
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iowrite32be(tmp, ®s->command_config);
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}
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void fman_tgec_reset_filter_table(struct tgec_regs *regs)
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{
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uint32_t i;
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for (i = 0; i < 512; i++)
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iowrite32be(i & ~TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl);
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}
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void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc)
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{
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uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */
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iowrite32be(hash | TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl);
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}
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void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value)
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{
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iowrite32be(value, ®s->hashtable_ctrl);
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}
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void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time)
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{
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iowrite32be((uint32_t)pause_time, ®s->pause_quant);
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}
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void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en)
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{
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uint32_t tmp;
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tmp = ioread32be(®s->command_config);
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if (en)
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tmp |= CMD_CFG_PAUSE_IGNORE;
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else
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tmp &= ~CMD_CFG_PAUSE_IGNORE;
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iowrite32be(tmp, ®s->command_config);
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}
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void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en)
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{
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uint32_t tmp;
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tmp = ioread32be(®s->command_config);
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if (en)
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tmp |= CMD_CFG_EN_TIMESTAMP;
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else
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tmp &= ~CMD_CFG_EN_TIMESTAMP;
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iowrite32be(tmp, ®s->command_config);
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}
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uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask)
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{
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return ioread32be(®s->ievent) & ev_mask;
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}
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void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask)
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{
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iowrite32be(ev_mask, ®s->ievent);
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}
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uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs)
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{
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return ioread32be(®s->imask);
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}
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void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *adr)
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{
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uint32_t tmp0, tmp1;
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tmp0 = (uint32_t)(adr[0] |
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adr[1] << 8 |
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adr[2] << 16 |
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adr[3] << 24);
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tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
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iowrite32be(tmp0, ®s->mac_addr_2);
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iowrite32be(tmp1, ®s->mac_addr_3);
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}
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void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs)
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{
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iowrite32be(0, ®s->mac_addr_2);
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iowrite32be(0, ®s->mac_addr_3);
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}
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uint32_t fman_tgec_get_revision(struct tgec_regs *regs)
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{
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return ioread32be(®s->tgec_id);
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}
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void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
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{
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iowrite32be(ioread32be(®s->imask) | ev_mask, ®s->imask);
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}
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void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
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{
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iowrite32be(ioread32be(®s->imask) & ~ev_mask, ®s->imask);
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}
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uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs)
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{
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return (uint16_t) ioread32be(®s->maxfrm);
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}
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void fman_tgec_defconfig(struct tgec_cfg *cfg)
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{
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cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE;
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cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE;
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cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE;
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cfg->pause_ignore = DEFAULT_PAUSE_IGNORE;
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cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE;
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cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE;
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cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE;
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cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD;
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cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE;
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cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE;
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cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR;
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cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE;
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cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
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cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
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cfg->pause_quant = DEFAULT_PAUSE_QUANT;
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#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
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cfg->skip_fman11_workaround = FALSE;
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#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
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}
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int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg,
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uint32_t exception_mask)
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{
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uint32_t tmp;
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/* Config */
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tmp = 0x40; /* CRC forward */
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if (cfg->wan_mode_enable)
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tmp |= CMD_CFG_WAN_MODE;
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if (cfg->promiscuous_mode_enable)
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tmp |= CMD_CFG_PROMIS_EN;
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if (cfg->pause_forward_enable)
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tmp |= CMD_CFG_PAUSE_FWD;
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if (cfg->pause_ignore)
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tmp |= CMD_CFG_PAUSE_IGNORE;
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if (cfg->tx_addr_ins_enable)
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tmp |= CMD_CFG_TX_ADDR_INS;
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if (cfg->loopback_enable)
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tmp |= CMD_CFG_LOOPBACK_EN;
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if (cfg->cmd_frame_enable)
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tmp |= CMD_CFG_CMD_FRM_EN;
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if (cfg->rx_error_discard)
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tmp |= CMD_CFG_RX_ER_DISC;
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if (cfg->send_idle_enable)
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tmp |= CMD_CFG_SEND_IDLE;
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if (cfg->no_length_check_enable)
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tmp |= CMD_CFG_NO_LEN_CHK;
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if (cfg->time_stamp_enable)
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tmp |= CMD_CFG_EN_TIMESTAMP;
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iowrite32be(tmp, ®s->command_config);
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/* Max Frame Length */
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iowrite32be((uint32_t)cfg->max_frame_length, ®s->maxfrm);
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/* Pause Time */
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iowrite32be(cfg->pause_quant, ®s->pause_quant);
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/* clear all pending events and set-up interrupts */
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fman_tgec_ack_event(regs, 0xffffffff);
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fman_tgec_enable_interrupt(regs, exception_mask);
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return 0;
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}
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void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs)
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{
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uint32_t tmp;
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/* restore the default tx ipg Length */
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tmp = (ioread32be(®s->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12;
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iowrite32be(tmp, ®s->tx_ipg_len);
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}
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