111 lines
5.5 KiB
C
111 lines
5.5 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/******************************************************************************
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@File memac.h
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@Description FM Multirate Ethernet MAC (mEMAC)
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*//***************************************************************************/
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#ifndef __MEMAC_H
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#define __MEMAC_H
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#include "std_ext.h"
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#include "error_ext.h"
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#include "list_ext.h"
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#include "fsl_fman_memac_mii_acc.h"
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#include "fm_mac.h"
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#include "fsl_fman_memac.h"
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#define MEMAC_default_exceptions \
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((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI))
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#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
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case e_FM_MAC_EX_10G_1TX_ECC_ER: \
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bitMask = MEMAC_IMASK_TECC_ER; break; \
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case e_FM_MAC_EX_10G_RX_ECC_ER: \
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bitMask = MEMAC_IMASK_RECC_ER; break; \
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case e_FM_MAC_EX_TS_FIFO_ECC_ERR: \
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bitMask = MEMAC_IMASK_TSECC_ER; break; \
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case e_FM_MAC_EX_MAGIC_PACKET_INDICATION: \
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bitMask = MEMAC_IMASK_MGI; break; \
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default: bitMask = 0;break;}
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typedef struct
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{
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t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
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t_Handle h_App; /**< Handle to the upper layer application */
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struct memac_regs *p_MemMap; /**< Pointer to MAC memory mapped registers */
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struct memac_mii_access_mem_map *p_MiiMemMap; /**< Pointer to MII memory mapped registers */
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uint64_t addr; /**< MAC address of device */
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e_EnetMode enetMode; /**< Ethernet physical interface */
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t_FmMacExceptionCallback *f_Exception;
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int mdioIrq;
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t_FmMacExceptionCallback *f_Event;
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bool indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
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uint64_t paddr[MEMAC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
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uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
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t_EthHash *p_MulticastAddrHash; /**< Pointer to driver's global address hash table */
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t_EthHash *p_UnicastAddrHash; /**< Pointer to driver's individual address hash table */
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bool debugMode;
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uint8_t macId;
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uint32_t exceptions;
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struct memac_cfg *p_MemacDriverParam;
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} t_Memac;
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/* Internal PHY access */
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#define PHY_MDIO_ADDR 0
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/* Internal PHY Registers - SGMII */
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#define PHY_SGMII_CR_PHY_RESET 0x8000
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#define PHY_SGMII_CR_RESET_AN 0x0200
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#define PHY_SGMII_CR_DEF_VAL 0x1140
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#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
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#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
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#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
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#define PHY_SGMII_IF_MODE_AN 0x0002
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#define PHY_SGMII_IF_MODE_SGMII 0x0001
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#define PHY_SGMII_IF_MODE_1000X 0x0000
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#define MEMAC_TO_MII_OFFSET 0x030 /* Offset from the MEM map to the MDIO mem map */
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t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data);
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t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
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#endif /* __MEMAC_H */
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