140 lines
5.1 KiB
C
140 lines
5.1 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "error_ext.h"
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#include "std_ext.h"
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#include "fm_mac.h"
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#include "tgec.h"
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#include "xx_ext.h"
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#include "fm_common.h"
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/*****************************************************************************/
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t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
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uint8_t phyAddr,
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uint8_t reg,
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uint16_t data)
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{
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t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
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t_TgecMiiAccessMemMap *p_MiiAccess;
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uint32_t cfgStatusReg;
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SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
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SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
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p_MiiAccess = p_Tgec->p_MiiMemMap;
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/* Configure MII */
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cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
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cfgStatusReg &= ~MIIMCOM_DIV_MASK;
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/* (one half of fm clock => 2.5Mhz) */
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cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
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WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
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WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_data, data);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
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XX_UDelay (1);
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return E_OK;
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}
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/*****************************************************************************/
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t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
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uint8_t phyAddr,
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uint8_t reg,
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uint16_t *p_Data)
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{
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t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
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t_TgecMiiAccessMemMap *p_MiiAccess;
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uint32_t cfgStatusReg;
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SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
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SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
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p_MiiAccess = p_Tgec->p_MiiMemMap;
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/* Configure MII */
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cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
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cfgStatusReg &= ~MIIMCOM_DIV_MASK;
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/* (one half of fm clock => 2.5Mhz) */
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cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
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WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
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WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
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XX_UDelay (1);
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*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
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cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
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if (cfgStatusReg & MIIMIND_READ_ERROR)
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RETURN_ERROR(MINOR, E_INVALID_VALUE,
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("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
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((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));
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return E_OK;
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}
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