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gcc14: fix internal compiler error on aarch64

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- https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501
- https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118892
- https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133
This commit is contained in:
Pavol Rusnak 2025-04-13 14:34:48 +02:00
parent cd0fbfaa99
commit 167ef04170
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GPG Key ID: 91F3B339B9A02A3D
2 changed files with 92 additions and 0 deletions
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87
pkgs/development/compilers/gcc/patches/14/aarch64-fix-ice-subreg.patch Normal file
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@ -0,0 +1,87 @@
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d3c381e82ce..6a481059bf0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6161,8 +6161,8 @@
(match_dup 1))
(match_dup 2))]
{
- operands[2] = lowpart_subreg (<GPI:MODE>mode, operands[2],
- <ALLX:MODE>mode);
+ operands[2] = force_lowpart_subreg (<GPI:MODE>mode, operands[2],
+ <ALLX:MODE>mode);
}
[(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
(set_attr "arch" "*,simd,simd")]
@@ -7210,7 +7210,7 @@
emit_insn (gen_iorv2<v_int_equiv>3 (
lowpart_subreg (V2<V_INT_EQUIV>mode, operands[0], <MODE>mode),
- lowpart_subreg (V2<V_INT_EQUIV>mode, operands[1], <MODE>mode),
+ force_lowpart_subreg (V2<V_INT_EQUIV>mode, operands[1], <MODE>mode),
v_bitmask));
DONE;
}
@@ -7255,8 +7255,8 @@
"TARGET_SIMD"
{
rtx tmp = gen_reg_rtx (<VCONQ>mode);
- rtx op1 = lowpart_subreg (<VCONQ>mode, operands[1], <MODE>mode);
- rtx op2 = lowpart_subreg (<VCONQ>mode, operands[2], <MODE>mode);
+ rtx op1 = force_lowpart_subreg (<VCONQ>mode, operands[1], <MODE>mode);
+ rtx op2 = force_lowpart_subreg (<VCONQ>mode, operands[2], <MODE>mode);
emit_insn (gen_xorsign3 (<VCONQ>mode, tmp, op1, op2));
emit_move_insn (operands[0],
lowpart_subreg (<MODE>mode, tmp, <VCONQ>mode));
diff --git a/gcc/explow.cc b/gcc/explow.cc
index f6843398c4b..80f59418bca 100644
--- a/gcc/explow.cc
+++ b/gcc/explow.cc
@@ -760,6 +760,34 @@ force_subreg (machine_mode outermode, rtx op,
return simplify_gen_subreg (outermode, op, innermode, byte);
}
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+ which has mode INNERMODE. Allow OP to be forced into a new register
+ if necessary.
+
+ Return null on failure. */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+ machine_mode innermode)
+{
+ auto byte = subreg_lowpart_offset (outermode, innermode);
+ return force_subreg (outermode, op, innermode, byte);
+}
+
+/* Try to return an rvalue expression for the OUTERMODE highpart of OP,
+ which has mode INNERMODE. Allow OP to be forced into a new register
+ if necessary.
+
+ Return null on failure. */
+
+rtx
+force_highpart_subreg (machine_mode outermode, rtx op,
+ machine_mode innermode)
+{
+ auto byte = subreg_highpart_offset (outermode, innermode);
+ return force_subreg (outermode, op, innermode, byte);
+}
+
/* If X is a memory ref, copy its contents to a new temp reg and return
that reg. Otherwise, return X. */
diff --git a/gcc/explow.h b/gcc/explow.h
index cbd1fcb7eb3..de89e9e2933 100644
--- a/gcc/explow.h
+++ b/gcc/explow.h
@@ -43,6 +43,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
extern rtx force_reg (machine_mode, rtx);
extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+extern rtx force_highpart_subreg (machine_mode, rtx, machine_mode);
/* Return given rtx, copied into a new temp reg if it was in memory. */
extern rtx force_not_mem (rtx);

5
pkgs/development/compilers/gcc/patches/default.nix
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@ -94,6 +94,11 @@ in
++ optional langD ./libphobos.patch
++ optional (!atLeast14) ./cfi_startproc-reorder-label-09-1.diff
++ optional (atLeast14 && !canApplyIainsDarwinPatches) ./cfi_startproc-reorder-label-14-1.diff
# backports of https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501
# and https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118892
# and https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133
# (hopefully all three will be included in the upcoming 14.3.0 release)
++ optional is14 ./14/aarch64-fix-ice-subreg.patch
## 2. Patches relevant to gcc>=12 on specific platforms ####################################