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15 lines
691 B
Plaintext
15 lines
691 B
Plaintext
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ChipVault is a VHDL and Verilog Chip Design Organization tool which improves
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design efficiency by:
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- Providing the ability to Navigate and Edit files Hierarchically.
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- Automatically generating Schematic Component Port views of VHDL and
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Verilog RTL files.
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- Automating RTL instantiation and template generation.
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- Providing Revision Control (designed for HW, not SW development).
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- Supporting External Tool Hooks (bottom-up vcoms,etc).
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- Providing an Issue Tracking Log with sorting.
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- Providing Netlist sorting and hierarchy viewing.
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- Supporting web-sharing of RTL files (both encrypted and clear).
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- Fast and Nimble.
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WWW: http://chipvault.sourceforge.net/
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