open source. It includes components for 3D surface and solid modeling,
visualization, data exchange and rapid application development.
Open CASCADE Technology can be best applied in development of numerical
simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM
applications.
BUGS: the module WOK does not work, but the other modules (the most
interesting parts) are OK.
Two distfiles (ccx_1.6.src.tar.bz2 cgx_1.6.all.tar.bz2)
are rerolled without changing filename.
Changes in ccx_1.6.src.tar.bz2
According to ccx_1.6/src/LOG-BOOK:
> 22 Feb 2006 - corrected an error in mafillsm.f
> 25 Feb 2006 - made a change in map3dto1d2d.f, arpack.c and arpackcs.c
> (rotational speed needed for stiffness matrix in
> frequency calculations)
Changes in cgx_1.6.all.tar.bz2
All are just minor fixes.
Spotted by: kris
'hostname nor servname provided, or not known', thus hopefully fix the
build of french/aster, which calls astk-serveur during its post-config.
Reported by: pointyhat via Kris
a graphical waveform viewer and a source level debugger. It also aims at
VHDL-93 compliancy. The project is at a very early development stage.
WWW: http://www.freehdl.seul.org/
PR: ports/104634
Submitted by: lon_kamikaze at gmx.de
- various manual updates
- update the INSTALL documentation
- fix a bug where pins turned into pure holes when an element
was smashed.
- use locale-independent strtod and dtostr functions to avoid problems
loading files saved in some locales.
- fixed various bugs which caused pcb to crash
- update the gtk status line after save/save as
- make the gerber file names be compatible with pre-HID versions
- split plated and unplated drill output
- fix various typos in menus and comments
- add a batch mode HID.
- fix drawing of box around text in the buffer
- various fixes and improvements to the trace optimizer and the
autorouter
- fix board flipping code
- fix rounding bug when creating list of drill sizes
- add support for > 8 copper layers
- avoid strict aliasing violations encountered with gcc4
- refactor code related to handling the filenames in the export
HID's
- fix layer group parsing code
- add the ability to user-configure mouse actions in the lesstif GUI.
- enable loaded netlists by default
- improve the positioning of the drill list in the postscript output
- various improvements to the configure script to improve robustness
and improve error messages when thing don't go well.
- add IPC style footprints for 01005 passives.
- added a Renumber() action which will renumber all reference designators
and produced an annotation file for backannotating to schematics.
- Draw via annulii on assembly drawings
- various other bug fixes and improvements.
many forms of circuit design, including:
- Custom IC layout (ASICs)
- Schematic drawing
- Hardware description language specifications
Author: Static Free Software & Sun Microsystems, Inc.
WWW: http://www.staticfreesoft.com/
PR: ports/100355
Submitted by: me (stas)
Approved by: sem (mentor)
simulation engines: GNU-Cap and Ng-Spice.
Current features:
Import gschem schematic files using gentlist.
Load and parse circuit description (net list) files.
Provides a GUI interface for GNU-Cap OP, DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
Provides a GUI interface for Ng-Spice DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
The raw output may be viewed for any processes initiated by gspiceui.
Formatting of simulator output so that it may be plotted using gwave.
WWW: http://www.geda.seul.org/tools/gspiceui/index.html
PR: ports/99357
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
specified in high-level description language into ready-to-compile c code for
the API of spice simulators.
WWW: http://mot-adms.sourceforge.net/
PR: ports/101014
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
working with superconducting Josephson junction circuits, yet the program
has the flexibility and power to meet the needs of other technologies.
Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
features. One added feature is a built-in graphical input front end for
schematic capture. While displayed, simulations can be run and data
plotted through this graphical interface.
While not as powerful or as pretty as the Xic graphical interface, it
holds its own in functionality.
A significantly enhanced output plotting capability is provided, and
Jspice3 has enhanced script interpretation capability.
WWW: http://www.wrcad.com/jspice3.html
PR: ports/93958
Submitted by: Pedro F. Giffuni
Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
** 20060414
- This is the first snapshot of the new HID version of PCB. HID, which
stands for Human Interface Device is the abstraction created by
DJ Delorie which seperates the core PCB code from the graphical user
interface. In this release, two GUI HID's are supported, gtk and lesstif.
In addition, there are HID exporters for postscript and encapsulated
postscript, RS-274-X (gerber), bill of materials, centroid file, and
png/gif/jpeg. This represents a major restructuring of the code and
many months of work.
- PCB's actions (the commands which drive the core of the program and
may be directly accessed by the user) now have the documentation in-line
in the code and the actions reference section of the manual is
extracted from the in-line documentation. The goal it to provide more
complete and accurate documentation. As always the manual is still
a work in progress but it is getting more complete and up to date.
- Fixed a long standing segfault when saving connection data
- Fixed a DRC bug
- Fix some rounding issues when setting sizes. Hopefully this will address
the issue with 23.99 mil drills and related problems.
- The html manual is now in one file instead of many files
- The lesstif HID now supports loading of background images to help
recover a layout which may exist in hardcopy form only.
** 20060321
- Add internal support for more than 8 layers. By default PCB is still
compiled for 8 copper layers.
- Fixed several minor bugs in the GTK user interface including fixing
scrolling of the log window, fixed up some of the DRC reporting
and mm/mil units.
- Fixed several key bindings.
- Updated refcard.tex to reflect the current set of key bindings.
- Fixed some minor bugs which caused compilation problems on some
systems.
- Converted the QFN footprints to hi-res.
- Added documentation to the manual for the centroid file format and
the algorithm used for finding the centroid and rotation.
- Fixed a bug so that the initial layer named 'component' is actually
on the component side of the board and 'solder' is actually on the
solder side of the board.
- Fixed the pin order in the bourns trim pots (~bourns library)
- Added actions and a script to allow command line printing.
- Added IPC-7351 recommended footprints for 0201, 0402, etc passives.
- Fixed SME5 package.
- Fixed a bug which prevented disabling nets from the ratsnest
- Fixed a bug where clearances could be set 1 below the spacing
- Fixed clearline flag so that arcs also have this property.
- Speed up rtree searches and other autorouter speedups.
- Fixed a bug in computation of the closest polygon point.
- Use rtrees for polygon handling for speed improvements.
- Add a ChangePinName() action.
- Fix a bug which caused duplicate rats names when manually adding
rats lines.
- Added DRC checks for minimum drill diameter and minimum annular ring.
- Add a minimal glossary to the manual
- Fix the author name in the fab drawing
- Cause the crosshair to snap to pad ends instead of center for rat
drawing.
- Add "join" to SetFlag, ClrFlag and ChangeFlag.
- Added inline documentation for the pcb file syntax. The manual now
is up to date and correctly documents the file format. In addition
the inline documentation will make it much easier to maintain the
documentation.
- Remove some broken m4lib footprints
- Put the correct setting for the gschem footprint= attribute in []
in the library window for the m4 libraries.
Submitted by: Stanislav Sedov (ssedov at mbsd dot msk dot ru)
PR: ports/99942
This release has several notable enhancements, including the
addition of a new example geometry model of a toy vehicle. The DXF
converter received considerable attention with the addition of
support for most of the formerly unsupported 2D entities. Several
bugs were identified and fixed in mged, g2asc, g_diff, and asc-nmg.
Documentation was improved for dbupgrade and dxf-g, and a new g-var
tool was created to facilitate conversion of models for purposes
directly related to OpenGL display lists. Finally, the new archer
modeling tool received support for multi-select and cut-n-paste.
PR: ports/99819
Submitted by: maintainer
1) gTAG - USB to JTAG interface
2) lightning_detector - a lightning detector
3) RF_Amp - schematics and associated materials for a SPICE model
4) TwoStageAmp - a two stage amplifier SPICE playpen
WWW: http://www.geda.seul.org
PR: ports/99564
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
the Tcl/Tk scripting language. The project is open-source (BSD license)
and based upon the NG-Spice source code base with many improvements
Features and Improvements
- Fully Tcl scriptable - installs with 'package require spice' statement
- Hspice syntax (SpicePP).
- GUI interfaces, various (Tk).
- SpiceWish (BLT graph widget)
- BLT (tcl compatible) vectors for storage, manipulation and arithmetic
upon Spice waveforms.
- Xspice additions (Georgia Tech).
- Trigger upon waveform events.
- Spice 'simulator state' save and restore for rapid 'what-if' simulations
(no longer need to re-simulate from the beginning each time a
device value is changed).
Author: Stefan Jones <stefan.jones@multigig.com>
WWW: http://tclspice.sourceforge.net/
PR: ports/99399
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
Those spaces used to hinder searching for the corresponding files
with portsearch -f '/FILENAME$' for obvious reasons.
Although currently portsearch removes those spaces itself remove
them anyway.
Inspired by: ports/94078
Approved by: portmgr (during freeze: krion, then kris advised to wait; at present: erwin)
This is a FEA program used in a classic FEM book. A complete (commercial)
version is available here:
<http://www.ce.berkeley.edu/~rlt/feap/>
The "personal version" is very limited, but it keeps the same format as
the complete (commercial) version and cad/netgen can produce files for it.
PR: ports/95210
Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
- Add an entry in ports/LEGAL;
- Clean up the port;
- Make pkg-descr look pretty and make some sligth adjustments to pkg-plist.
PR: 93879
Submitted by: Daniel Thiele <dthiele (at) gmx.net> (maintainer)
partitioning, static mapping, and sparse matrix block ordering.
Its purpose of Scotch is to apply graph theory, with a divide and conquer
approach, to scientific computing problems such as graph and mesh partitioning,
static mapping, and sparse matrix ordering, in application domains ranging from
structural mechanics to operating systems or bio-chemistry.
Note: there is an older tarball included in Aster's distfile, but I prefer
a separate distfile from the official site.
- Shared lib version and PORTREVISION bumb for all affected ports.
While I'm here:
- Remove USE_MESA knob where it was (35 ports).
It marked as depricated for 2 years.
PR: ports/90247
Submitted by: Ermal Lu?i <eri--@albabsd.org>
When I ported this I added amd64 to give the "benefit of
doubt" however I had the chance top test it but it doesn't
work, it coredumps.
PR: ports/91188
Submitted by: Pedro F. Giffuni <giffunip@asme.org>
Another version upgrade. The amd64 problem has been fixed,
both as a patch here and in the HEAD of the sf.net repository.
This has only been tested on 6.0/ia32 and 6.0/amd64, my 7
box is down and I don't have 4 or 5 anymore. :/
PR: ports/91037
Submitted by: Erik Greenwald <erik@smluc.org>
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
- Update to 27
- Use a static pkg-plist
- Pass maintainership to submitter
PR: ports/90818
Submitted by: Soeren Straarup <xride@x12.dk>
Submitted by: pointyhat (kris)
Pointy hat to: garga
diagrams and printed circuit board artwork.
Kicad is a set of four softwares and a project manager:
* Eeschema: Schematic entry.
* Pcbnew: Board editor.
* Gerbview: GERBER viewer (photoplotter documents).
* Cvpcb: footprint selector for components used in the circuit design.
* Kicad: project manager.
