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16 lines
766 B
Plaintext
16 lines
766 B
Plaintext
Icarus Verilog is a Verilog simulation and synthesis tool. It
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operates as a compiler, compiling source code writen in Verilog
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(IEEE-1364) into some target format. For batch simulation, the
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compiler can generate C++ code that is compiled and linked with
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a run time library (called "vvm") then executed as a command to
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run the simulation. For synthesis, the compiler generates netlists
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in the desired format.
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The compiler proper is intended to parse and elaborate design
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descriptions written to the IEEE standard IEEE Std 1364-2000. The
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standard proper is due to be release towards the middle of the
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year 2000. This is a fairly large and complex standard, so it will
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take some time for it to get there, but that's the goal.
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WWW: http://www.icarus.com/eda/verilog/
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