Michael Reifenberger 55caf84116 Enable experimental features. ... Make portlint happy. Mark Broken for FreeBSD 10 due to compile/link error.		2018-04-25 16:29:09 +00:00
..
abc	New port: cad/abc: System for sequential synthesis and verification	2018-04-24 07:53:29 +00:00
admesh
adms
alliance
astk-client
astk-serveur
atlc
basicdsp
brickutils
brlcad
calculix
calculix-ccx
cascade
chipvault
cider
cura-engine
dinotrace
dxf2fig
electric
electric-ng
elmerfem
feappv
fidocadj
freecad	- Update to 0.17.13509	2018-04-22 06:24:25 +00:00
freehdl
fritzing
gdsreader
gdt
geda
gerbv
ghdl
gmsh
gmsh-occ
gnucap
gplcver
gspiceui
gtkwave
impact
irsim
iverilog
jspice3
kicad
kicad-devel	Add missing distinfo changes	2018-04-22 13:52:01 +00:00
kicad-library
kicad-library-devel
klayout
layouteditor
ldraw
leocad
libopencad
librecad
linux-eagle5
linuxcnc-devel
logisim
magic
meshdev
meshlab
NASTRAN-95
netgen
ngspice_rework
opencascade
openscad	Add openscad-devel to the build and register conflict.	2018-04-22 18:16:02 +00:00
openscad-devel	Enable experimental features.	2018-04-25 16:29:09 +00:00
openvsp
p5-GDS2
p5-Verilog-Perl
pcb
pdnmesh
py-gdspy
py-lcapy
py-pycam
py-pyfda
python-gdsii
pythoncad
qcad
qelectrotech
qfsm
qmls
qucs
repsnapper
rubygem-gdsii
sceptre
scotch
solvespace
sp2sp
spice
stepcode
sumo
sweethome3d
tkgate
tochnog
transcalc
varkon
verilog-mode.el
xcircuit
z88
zcad
Makefile	New port: cad/abc: System for sequential synthesis and verification	2018-04-24 07:53:29 +00:00