mirror of
https://git.FreeBSD.org/ports.git
synced 2024-12-10 02:45:11 +00:00
74f0872c5b
A project organizer for VHDL and Verilog RTL hardware designs
15 lines
691 B
Plaintext
15 lines
691 B
Plaintext
ChipVault is a VHDL and Verilog Chip Design Organization tool which improves
|
|
design efficiency by:
|
|
- Providing the ability to Navigate and Edit files Hierarchically.
|
|
- Automatically generating Schematic Component Port views of VHDL and
|
|
Verilog RTL files.
|
|
- Automating RTL instantiation and template generation.
|
|
- Providing Revision Control (designed for HW, not SW development).
|
|
- Supporting External Tool Hooks (bottom-up vcoms,etc).
|
|
- Providing an Issue Tracking Log with sorting.
|
|
- Providing Netlist sorting and hierarchy viewing.
|
|
- Supporting web-sharing of RTL files (both encrypted and clear).
|
|
- Fast and Nimble.
|
|
|
|
WWW: http://chipvault.sourceforge.net/
|